[X86] Use __builtin_convertvector to implement some of the packed integer to packed float conversion intrinsics.

I believe this is safe assuming default default FP environment. The conversion might be inexact, but it can never overflow the FP type so this shouldn't be undefined behavior for the uitofp/sitofp instructions.

We already do something similar for scalar conversions.

Differential Revision: https://reviews.llvm.org/D46863

llvm-svn: 332882
This commit is contained in:
Craig Topper 2018-05-21 20:19:17 +00:00
parent 9a45114b3c
commit 842171de36
14 changed files with 128 additions and 152 deletions

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@ -320,7 +320,6 @@ TARGET_BUILTIN(__builtin_ia32_movnti, "vi*i", "n", "sse2")
TARGET_BUILTIN(__builtin_ia32_psadbw128, "V2LLiV16cV16c", "nc", "sse2")
TARGET_BUILTIN(__builtin_ia32_sqrtpd, "V2dV2d", "nc", "sse2")
TARGET_BUILTIN(__builtin_ia32_sqrtsd, "V2dV2d", "nc", "sse2")
TARGET_BUILTIN(__builtin_ia32_cvtdq2ps, "V4fV4i", "nc", "sse2")
TARGET_BUILTIN(__builtin_ia32_cvtpd2dq, "V2LLiV2d", "nc", "sse2")
TARGET_BUILTIN(__builtin_ia32_cvtpd2ps, "V4fV2d", "nc", "sse2")
TARGET_BUILTIN(__builtin_ia32_cvttpd2dq, "V4iV2d", "nc", "sse2")
@ -1200,8 +1199,6 @@ TARGET_BUILTIN(__builtin_ia32_cvttpd2udq128_mask, "V4iV2dV4iUc", "nc", "avx512vl
TARGET_BUILTIN(__builtin_ia32_cvttpd2udq256_mask, "V4iV4dV4iUc", "nc", "avx512vl")
TARGET_BUILTIN(__builtin_ia32_cvttps2udq128_mask, "V4iV4fV4iUc", "nc", "avx512vl")
TARGET_BUILTIN(__builtin_ia32_cvttps2udq256_mask, "V8iV8fV8iUc", "nc", "avx512vl")
TARGET_BUILTIN(__builtin_ia32_cvtudq2ps128_mask, "V4fV4iV4fUc", "nc", "avx512vl")
TARGET_BUILTIN(__builtin_ia32_cvtudq2ps256_mask, "V8fV8iV8fUc", "nc", "avx512vl")
TARGET_BUILTIN(__builtin_ia32_expanddf128_mask, "V2dV2dV2dUc", "nc", "avx512vl")
TARGET_BUILTIN(__builtin_ia32_expanddf256_mask, "V4dV4dV4dUc", "nc", "avx512vl")
TARGET_BUILTIN(__builtin_ia32_expanddi128_mask, "V2LLiV2LLiV2LLiUc", "nc", "avx512vl")
@ -1363,8 +1360,6 @@ TARGET_BUILTIN(__builtin_ia32_cvtps2qq128_mask, "V2LLiV4fV2LLiUc", "nc", "avx512
TARGET_BUILTIN(__builtin_ia32_cvtps2qq256_mask, "V4LLiV4fV4LLiUc", "nc", "avx512vl,avx512dq")
TARGET_BUILTIN(__builtin_ia32_cvtps2uqq128_mask, "V2LLiV4fV2LLiUc", "nc", "avx512vl,avx512dq")
TARGET_BUILTIN(__builtin_ia32_cvtps2uqq256_mask, "V4LLiV4fV4LLiUc", "nc", "avx512vl,avx512dq")
TARGET_BUILTIN(__builtin_ia32_cvtqq2pd128_mask, "V2dV2LLiV2dUc", "nc", "avx512vl,avx512dq")
TARGET_BUILTIN(__builtin_ia32_cvtqq2pd256_mask, "V4dV4LLiV4dUc", "nc", "avx512vl,avx512dq")
TARGET_BUILTIN(__builtin_ia32_cvtqq2ps128_mask, "V4fV2LLiV4fUc", "nc", "avx512vl,avx512dq")
TARGET_BUILTIN(__builtin_ia32_cvtqq2ps256_mask, "V4fV4LLiV4fUc", "nc", "avx512vl,avx512dq")
TARGET_BUILTIN(__builtin_ia32_cvttpd2qq128_mask, "V2LLiV2dV2LLiUc", "nc", "avx512vl,avx512dq")
@ -1375,8 +1370,6 @@ TARGET_BUILTIN(__builtin_ia32_cvttps2qq128_mask, "V2LLiV4fV2LLiUc", "nc", "avx51
TARGET_BUILTIN(__builtin_ia32_cvttps2qq256_mask, "V4LLiV4fV4LLiUc", "nc", "avx512vl,avx512dq")
TARGET_BUILTIN(__builtin_ia32_cvttps2uqq128_mask, "V2LLiV4fV2LLiUc", "nc", "avx512vl,avx512dq")
TARGET_BUILTIN(__builtin_ia32_cvttps2uqq256_mask, "V4LLiV4fV4LLiUc", "nc", "avx512vl,avx512dq")
TARGET_BUILTIN(__builtin_ia32_cvtuqq2pd128_mask, "V2dV2LLiV2dUc", "nc", "avx512vl,avx512dq")
TARGET_BUILTIN(__builtin_ia32_cvtuqq2pd256_mask, "V4dV4LLiV4dUc", "nc", "avx512vl,avx512dq")
TARGET_BUILTIN(__builtin_ia32_cvtuqq2ps128_mask, "V4fV2LLiV4fUc", "nc", "avx512vl,avx512dq")
TARGET_BUILTIN(__builtin_ia32_cvtuqq2ps256_mask, "V4fV4LLiV4fUc", "nc", "avx512vl,avx512dq")
TARGET_BUILTIN(__builtin_ia32_rangepd128_mask, "V2dV2dV2dIiV2dUc", "nc", "avx512vl,avx512dq")

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@ -361,26 +361,21 @@ _mm512_maskz_cvtps_epu64 (__mmask8 __U, __m256 __A) {
static __inline__ __m512d __DEFAULT_FN_ATTRS
_mm512_cvtepi64_pd (__m512i __A) {
return (__m512d) __builtin_ia32_cvtqq2pd512_mask ((__v8di) __A,
(__v8df) _mm512_setzero_pd(),
(__mmask8) -1,
_MM_FROUND_CUR_DIRECTION);
return (__m512d)__builtin_convertvector((__v8di)__A, __v8df);
}
static __inline__ __m512d __DEFAULT_FN_ATTRS
_mm512_mask_cvtepi64_pd (__m512d __W, __mmask8 __U, __m512i __A) {
return (__m512d) __builtin_ia32_cvtqq2pd512_mask ((__v8di) __A,
(__v8df) __W,
(__mmask8) __U,
_MM_FROUND_CUR_DIRECTION);
return (__m512d)__builtin_ia32_selectpd_512((__mmask8)__U,
(__v8df)_mm512_cvtepi64_pd(__A),
(__v8df)__W);
}
static __inline__ __m512d __DEFAULT_FN_ATTRS
_mm512_maskz_cvtepi64_pd (__mmask8 __U, __m512i __A) {
return (__m512d) __builtin_ia32_cvtqq2pd512_mask ((__v8di) __A,
(__v8df) _mm512_setzero_pd(),
(__mmask8) __U,
_MM_FROUND_CUR_DIRECTION);
return (__m512d)__builtin_ia32_selectpd_512((__mmask8)__U,
(__v8df)_mm512_cvtepi64_pd(__A),
(__v8df)_mm512_setzero_pd());
}
#define _mm512_cvt_roundepi64_pd(A, R) __extension__ ({ \
@ -596,26 +591,21 @@ _mm512_maskz_cvttps_epu64 (__mmask8 __U, __m256 __A) {
static __inline__ __m512d __DEFAULT_FN_ATTRS
_mm512_cvtepu64_pd (__m512i __A) {
return (__m512d) __builtin_ia32_cvtuqq2pd512_mask ((__v8di) __A,
(__v8df) _mm512_setzero_pd(),
(__mmask8) -1,
_MM_FROUND_CUR_DIRECTION);
return (__m512d)__builtin_convertvector((__v8du)__A, __v8df);
}
static __inline__ __m512d __DEFAULT_FN_ATTRS
_mm512_mask_cvtepu64_pd (__m512d __W, __mmask8 __U, __m512i __A) {
return (__m512d) __builtin_ia32_cvtuqq2pd512_mask ((__v8di) __A,
(__v8df) __W,
(__mmask8) __U,
_MM_FROUND_CUR_DIRECTION);
return (__m512d)__builtin_ia32_selectpd_512((__mmask8)__U,
(__v8df)_mm512_cvtepu64_pd(__A),
(__v8df)__W);
}
static __inline__ __m512d __DEFAULT_FN_ATTRS
_mm512_maskz_cvtepu64_pd (__mmask8 __U, __m512i __A) {
return (__m512d) __builtin_ia32_cvtuqq2pd512_mask ((__v8di) __A,
(__v8df) _mm512_setzero_pd(),
(__mmask8) __U,
_MM_FROUND_CUR_DIRECTION);
return (__m512d)__builtin_ia32_selectpd_512((__mmask8)__U,
(__v8df)_mm512_cvtepu64_pd(__A),
(__v8df)_mm512_setzero_pd());
}
#define _mm512_cvt_roundepu64_pd(A, R) __extension__ ({ \

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@ -3831,28 +3831,23 @@ _mm512_maskz_cvttps_epu32 (__mmask16 __U, __m512 __A)
static __inline__ __m512 __DEFAULT_FN_ATTRS
_mm512_cvtepu32_ps (__m512i __A)
{
return (__m512) __builtin_ia32_cvtudq2ps512_mask ((__v16si) __A,
(__v16sf) _mm512_undefined_ps (),
(__mmask16) -1,
_MM_FROUND_CUR_DIRECTION);
return (__m512)__builtin_convertvector((__v16su)__A, __v16sf);
}
static __inline__ __m512 __DEFAULT_FN_ATTRS
_mm512_mask_cvtepu32_ps (__m512 __W, __mmask16 __U, __m512i __A)
{
return (__m512) __builtin_ia32_cvtudq2ps512_mask ((__v16si) __A,
(__v16sf) __W,
(__mmask16) __U,
_MM_FROUND_CUR_DIRECTION);
return (__m512)__builtin_ia32_selectps_512((__mmask16)__U,
(__v16sf)_mm512_cvtepu32_ps(__A),
(__v16sf)__W);
}
static __inline__ __m512 __DEFAULT_FN_ATTRS
_mm512_maskz_cvtepu32_ps (__mmask16 __U, __m512i __A)
{
return (__m512) __builtin_ia32_cvtudq2ps512_mask ((__v16si) __A,
(__v16sf) _mm512_setzero_ps (),
(__mmask16) __U,
_MM_FROUND_CUR_DIRECTION);
return (__m512)__builtin_ia32_selectps_512((__mmask16)__U,
(__v16sf)_mm512_cvtepu32_ps(__A),
(__v16sf)_mm512_setzero_ps());
}
static __inline __m512d __DEFAULT_FN_ATTRS
@ -3892,28 +3887,23 @@ _mm512_mask_cvtepi32lo_pd(__m512d __W, __mmask8 __U,__m512i __A)
static __inline__ __m512 __DEFAULT_FN_ATTRS
_mm512_cvtepi32_ps (__m512i __A)
{
return (__m512) __builtin_ia32_cvtdq2ps512_mask ((__v16si) __A,
(__v16sf) _mm512_undefined_ps (),
(__mmask16) -1,
_MM_FROUND_CUR_DIRECTION);
return (__m512)__builtin_convertvector((__v16si)__A, __v16sf);
}
static __inline__ __m512 __DEFAULT_FN_ATTRS
_mm512_mask_cvtepi32_ps (__m512 __W, __mmask16 __U, __m512i __A)
{
return (__m512) __builtin_ia32_cvtdq2ps512_mask ((__v16si) __A,
(__v16sf) __W,
(__mmask16) __U,
_MM_FROUND_CUR_DIRECTION);
return (__m512)__builtin_ia32_selectps_512((__mmask16)__U,
(__v16sf)_mm512_cvtepi32_ps(__A),
(__v16sf)__W);
}
static __inline__ __m512 __DEFAULT_FN_ATTRS
_mm512_maskz_cvtepi32_ps (__mmask16 __U, __m512i __A)
{
return (__m512) __builtin_ia32_cvtdq2ps512_mask ((__v16si) __A,
(__v16sf) _mm512_setzero_ps (),
(__mmask16) __U,
_MM_FROUND_CUR_DIRECTION);
return (__m512)__builtin_ia32_selectps_512((__mmask16)__U,
(__v16sf)_mm512_cvtepi32_ps(__A),
(__v16sf)_mm512_setzero_ps());
}
static __inline __m512d __DEFAULT_FN_ATTRS

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@ -463,44 +463,40 @@ _mm256_maskz_cvtps_epu64 (__mmask8 __U, __m128 __A) {
static __inline__ __m128d __DEFAULT_FN_ATTRS
_mm_cvtepi64_pd (__m128i __A) {
return (__m128d) __builtin_ia32_cvtqq2pd128_mask ((__v2di) __A,
(__v2df) _mm_setzero_pd(),
(__mmask8) -1);
return (__m128d)__builtin_convertvector((__v2di)__A, __v2df);
}
static __inline__ __m128d __DEFAULT_FN_ATTRS
_mm_mask_cvtepi64_pd (__m128d __W, __mmask8 __U, __m128i __A) {
return (__m128d) __builtin_ia32_cvtqq2pd128_mask ((__v2di) __A,
(__v2df) __W,
(__mmask8) __U);
return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
(__v2df)_mm_cvtepi64_pd(__A),
(__v2df)__W);
}
static __inline__ __m128d __DEFAULT_FN_ATTRS
_mm_maskz_cvtepi64_pd (__mmask8 __U, __m128i __A) {
return (__m128d) __builtin_ia32_cvtqq2pd128_mask ((__v2di) __A,
(__v2df) _mm_setzero_pd(),
(__mmask8) __U);
return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
(__v2df)_mm_cvtepi64_pd(__A),
(__v2df)_mm_setzero_pd());
}
static __inline__ __m256d __DEFAULT_FN_ATTRS
_mm256_cvtepi64_pd (__m256i __A) {
return (__m256d) __builtin_ia32_cvtqq2pd256_mask ((__v4di) __A,
(__v4df) _mm256_setzero_pd(),
(__mmask8) -1);
return (__m256d)__builtin_convertvector((__v4di)__A, __v4df);
}
static __inline__ __m256d __DEFAULT_FN_ATTRS
_mm256_mask_cvtepi64_pd (__m256d __W, __mmask8 __U, __m256i __A) {
return (__m256d) __builtin_ia32_cvtqq2pd256_mask ((__v4di) __A,
(__v4df) __W,
(__mmask8) __U);
return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
(__v4df)_mm256_cvtepi64_pd(__A),
(__v4df)__W);
}
static __inline__ __m256d __DEFAULT_FN_ATTRS
_mm256_maskz_cvtepi64_pd (__mmask8 __U, __m256i __A) {
return (__m256d) __builtin_ia32_cvtqq2pd256_mask ((__v4di) __A,
(__v4df) _mm256_setzero_pd(),
(__mmask8) __U);
return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
(__v4df)_mm256_cvtepi64_pd(__A),
(__v4df)_mm256_setzero_pd());
}
static __inline__ __m128 __DEFAULT_FN_ATTRS
@ -715,44 +711,40 @@ _mm256_maskz_cvttps_epu64 (__mmask8 __U, __m128 __A) {
static __inline__ __m128d __DEFAULT_FN_ATTRS
_mm_cvtepu64_pd (__m128i __A) {
return (__m128d) __builtin_ia32_cvtuqq2pd128_mask ((__v2di) __A,
(__v2df) _mm_setzero_pd(),
(__mmask8) -1);
return (__m128d)__builtin_convertvector((__v2du)__A, __v2df);
}
static __inline__ __m128d __DEFAULT_FN_ATTRS
_mm_mask_cvtepu64_pd (__m128d __W, __mmask8 __U, __m128i __A) {
return (__m128d) __builtin_ia32_cvtuqq2pd128_mask ((__v2di) __A,
(__v2df) __W,
(__mmask8) __U);
return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
(__v2df)_mm_cvtepu64_pd(__A),
(__v2df)__W);
}
static __inline__ __m128d __DEFAULT_FN_ATTRS
_mm_maskz_cvtepu64_pd (__mmask8 __U, __m128i __A) {
return (__m128d) __builtin_ia32_cvtuqq2pd128_mask ((__v2di) __A,
(__v2df) _mm_setzero_pd(),
(__mmask8) __U);
return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
(__v2df)_mm_cvtepu64_pd(__A),
(__v2df)_mm_setzero_pd());
}
static __inline__ __m256d __DEFAULT_FN_ATTRS
_mm256_cvtepu64_pd (__m256i __A) {
return (__m256d) __builtin_ia32_cvtuqq2pd256_mask ((__v4di) __A,
(__v4df) _mm256_setzero_pd(),
(__mmask8) -1);
return (__m256d)__builtin_convertvector((__v4du)__A, __v4df);
}
static __inline__ __m256d __DEFAULT_FN_ATTRS
_mm256_mask_cvtepu64_pd (__m256d __W, __mmask8 __U, __m256i __A) {
return (__m256d) __builtin_ia32_cvtuqq2pd256_mask ((__v4di) __A,
(__v4df) __W,
(__mmask8) __U);
return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
(__v4df)_mm256_cvtepu64_pd(__A),
(__v4df)__W);
}
static __inline__ __m256d __DEFAULT_FN_ATTRS
_mm256_maskz_cvtepu64_pd (__mmask8 __U, __m256i __A) {
return (__m256d) __builtin_ia32_cvtuqq2pd256_mask ((__v4di) __A,
(__v4df) _mm256_setzero_pd(),
(__mmask8) __U);
return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
(__v4df)_mm256_cvtepu64_pd(__A),
(__v4df)_mm256_setzero_pd());
}
static __inline__ __m128 __DEFAULT_FN_ATTRS

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@ -2207,48 +2207,40 @@ _mm256_maskz_cvtepu32_pd (__mmask8 __U, __m128i __A) {
static __inline__ __m128 __DEFAULT_FN_ATTRS
_mm_cvtepu32_ps (__m128i __A) {
return (__m128) __builtin_ia32_cvtudq2ps128_mask ((__v4si) __A,
(__v4sf)
_mm_setzero_ps (),
(__mmask8) -1);
return (__m128)__builtin_convertvector((__v4su)__A, __v4sf);
}
static __inline__ __m128 __DEFAULT_FN_ATTRS
_mm_mask_cvtepu32_ps (__m128 __W, __mmask8 __U, __m128i __A) {
return (__m128) __builtin_ia32_cvtudq2ps128_mask ((__v4si) __A,
(__v4sf) __W,
(__mmask8) __U);
return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
(__v4sf)_mm_cvtepu32_ps(__A),
(__v4sf)__W);
}
static __inline__ __m128 __DEFAULT_FN_ATTRS
_mm_maskz_cvtepu32_ps (__mmask8 __U, __m128i __A) {
return (__m128) __builtin_ia32_cvtudq2ps128_mask ((__v4si) __A,
(__v4sf)
_mm_setzero_ps (),
(__mmask8) __U);
return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
(__v4sf)_mm_cvtepu32_ps(__A),
(__v4sf)_mm_setzero_ps());
}
static __inline__ __m256 __DEFAULT_FN_ATTRS
_mm256_cvtepu32_ps (__m256i __A) {
return (__m256) __builtin_ia32_cvtudq2ps256_mask ((__v8si) __A,
(__v8sf)
_mm256_setzero_ps (),
(__mmask8) -1);
return (__m256)__builtin_convertvector((__v8su)__A, __v8sf);
}
static __inline__ __m256 __DEFAULT_FN_ATTRS
_mm256_mask_cvtepu32_ps (__m256 __W, __mmask8 __U, __m256i __A) {
return (__m256) __builtin_ia32_cvtudq2ps256_mask ((__v8si) __A,
(__v8sf) __W,
(__mmask8) __U);
return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
(__v8sf)_mm256_cvtepu32_ps(__A),
(__v8sf)__W);
}
static __inline__ __m256 __DEFAULT_FN_ATTRS
_mm256_maskz_cvtepu32_ps (__mmask8 __U, __m256i __A) {
return (__m256) __builtin_ia32_cvtudq2ps256_mask ((__v8si) __A,
(__v8sf)
_mm256_setzero_ps (),
(__mmask8) __U);
return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
(__v8sf)_mm256_cvtepu32_ps(__A),
(__v8sf)_mm256_setzero_ps());
}
static __inline__ __m128d __DEFAULT_FN_ATTRS

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@ -2225,7 +2225,7 @@ _mm256_cvtepi32_pd(__m128i __a)
static __inline __m256 __DEFAULT_FN_ATTRS
_mm256_cvtepi32_ps(__m256i __a)
{
return (__m256)__builtin_ia32_cvtdq2ps256((__v8si) __a);
return (__m256)__builtin_convertvector((__v8si)__a, __v8sf);
}
/// Converts a 256-bit vector of [4 x double] into a 128-bit vector of

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@ -3424,7 +3424,7 @@ _mm_cvttsd_si64(__m128d __a)
static __inline__ __m128 __DEFAULT_FN_ATTRS
_mm_cvtepi32_ps(__m128i __a)
{
return __builtin_ia32_cvtdq2ps((__v4si)__a);
return (__m128)__builtin_convertvector((__v4si)__a, __v4sf);
}
/// Converts a vector of [4 x float] into a vector of [4 x i32].

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@ -256,7 +256,7 @@ __m256d test_mm256_cvtepi32_pd(__m128i A) {
__m256 test_mm256_cvtepi32_ps(__m256i A) {
// CHECK-LABEL: test_mm256_cvtepi32_ps
// CHECK: call <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32> %{{.*}})
// CHECK: sitofp <8 x i32> %{{.*}} to <8 x float>
return _mm256_cvtepi32_ps(A);
}

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@ -347,19 +347,21 @@ __m512i test_mm512_maskz_cvt_roundps_epu64(__mmask8 __U, __m256 __A) {
__m512d test_mm512_cvtepi64_pd(__m512i __A) {
// CHECK-LABEL: @test_mm512_cvtepi64_pd
// CHECK: @llvm.x86.avx512.mask.cvtqq2pd.512
// CHECK: sitofp <8 x i64> %{{.*}} to <8 x double>
return _mm512_cvtepi64_pd(__A);
}
__m512d test_mm512_mask_cvtepi64_pd(__m512d __W, __mmask8 __U, __m512i __A) {
// CHECK-LABEL: @test_mm512_mask_cvtepi64_pd
// CHECK: @llvm.x86.avx512.mask.cvtqq2pd.512
// CHECK: sitofp <8 x i64> %{{.*}} to <8 x double>
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
return _mm512_mask_cvtepi64_pd(__W, __U, __A);
}
__m512d test_mm512_maskz_cvtepi64_pd(__mmask8 __U, __m512i __A) {
// CHECK-LABEL: @test_mm512_maskz_cvtepi64_pd
// CHECK: @llvm.x86.avx512.mask.cvtqq2pd.512
// CHECK: sitofp <8 x i64> %{{.*}} to <8 x double>
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
return _mm512_maskz_cvtepi64_pd(__U, __A);
}
@ -563,19 +565,21 @@ __m512i test_mm512_maskz_cvtt_roundps_epu64(__mmask8 __U, __m256 __A) {
__m512d test_mm512_cvtepu64_pd(__m512i __A) {
// CHECK-LABEL: @test_mm512_cvtepu64_pd
// CHECK: @llvm.x86.avx512.mask.cvtuqq2pd.512
// CHECK: uitofp <8 x i64> %{{.*}} to <8 x double>
return _mm512_cvtepu64_pd(__A);
}
__m512d test_mm512_mask_cvtepu64_pd(__m512d __W, __mmask8 __U, __m512i __A) {
// CHECK-LABEL: @test_mm512_mask_cvtepu64_pd
// CHECK: @llvm.x86.avx512.mask.cvtuqq2pd.512
// CHECK: uitofp <8 x i64> %{{.*}} to <8 x double>
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
return _mm512_mask_cvtepu64_pd(__W, __U, __A);
}
__m512d test_mm512_maskz_cvtepu64_pd(__mmask8 __U, __m512i __A) {
// CHECK-LABEL: @test_mm512_maskz_cvtepu64_pd
// CHECK: @llvm.x86.avx512.mask.cvtuqq2pd.512
// CHECK: uitofp <8 x i64> %{{.*}} to <8 x double>
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
return _mm512_maskz_cvtepu64_pd(__U, __A);
}

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@ -7085,21 +7085,23 @@ __m512i test_mm512_maskz_cvttps_epu32 (__mmask16 __U, __m512 __A)
__m512 test_mm512_cvtepu32_ps (__m512i __A)
{
// CHECK-LABEL: @test_mm512_cvtepu32_ps
// CHECK: @llvm.x86.avx512.mask.cvtudq2ps.512
// CHECK: uitofp <16 x i32> %{{.*}} to <16 x float>
return _mm512_cvtepu32_ps (__A);
}
__m512 test_mm512_mask_cvtepu32_ps (__m512 __W, __mmask16 __U, __m512i __A)
{
// CHECK-LABEL: @test_mm512_mask_cvtepu32_ps
// CHECK: @llvm.x86.avx512.mask.cvtudq2ps.512
// CHECK: uitofp <16 x i32> %{{.*}} to <16 x float>
// CHECK: select <16 x i1> {{.*}}, <16 x float> {{.*}}, <16 x float> {{.*}}
return _mm512_mask_cvtepu32_ps (__W,__U,__A);
}
__m512 test_mm512_maskz_cvtepu32_ps (__mmask16 __U, __m512i __A)
{
// CHECK-LABEL: @test_mm512_maskz_cvtepu32_ps
// CHECK: @llvm.x86.avx512.mask.cvtudq2ps.512
// CHECK: uitofp <16 x i32> %{{.*}} to <16 x float>
// CHECK: select <16 x i1> {{.*}}, <16 x float> {{.*}}, <16 x float> {{.*}}
return _mm512_maskz_cvtepu32_ps (__U,__A);
}
@ -7146,21 +7148,23 @@ __m512d test_mm512_mask_cvtepi32lo_pd (__m512d __W, __mmask8 __U, __m512i __A)
__m512 test_mm512_cvtepi32_ps (__m512i __A)
{
// CHECK-LABEL: @test_mm512_cvtepi32_ps
// CHECK: @llvm.x86.avx512.mask.cvtdq2ps.512
// CHECK: sitofp <16 x i32> %{{.*}} to <16 x float>
return _mm512_cvtepi32_ps (__A);
}
__m512 test_mm512_mask_cvtepi32_ps (__m512 __W, __mmask16 __U, __m512i __A)
{
// CHECK-LABEL: @test_mm512_mask_cvtepi32_ps
// CHECK: @llvm.x86.avx512.mask.cvtdq2ps.512
// CHECK: sitofp <16 x i32> %{{.*}} to <16 x float>
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
return _mm512_mask_cvtepi32_ps (__W,__U,__A);
}
__m512 test_mm512_maskz_cvtepi32_ps (__mmask16 __U, __m512i __A)
{
// CHECK-LABEL: @test_mm512_maskz_cvtepi32_ps
// CHECK: @llvm.x86.avx512.mask.cvtdq2ps.512
// CHECK: sitofp <16 x i32> %{{.*}} to <16 x float>
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
return _mm512_maskz_cvtepi32_ps (__U,__A);
}

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@ -1791,25 +1791,25 @@ __m256d test_mm256_maskz_cvtepi32_pd(__mmask8 __U, __m128i __A) {
}
__m128 test_mm_mask_cvtepi32_ps(__m128 __W, __mmask8 __U, __m128i __A) {
// CHECK-LABEL: @test_mm_mask_cvtepi32_ps
// CHECK: @llvm.x86.sse2.cvtdq2ps
// CHECK: sitofp <4 x i32> %{{.*}} to <4 x float>
// CHECK: select <4 x i1> {{.*}}, <4 x float> {{.*}}, <4 x float> {{.*}}
return _mm_mask_cvtepi32_ps(__W,__U,__A);
}
__m128 test_mm_maskz_cvtepi32_ps(__mmask16 __U, __m128i __A) {
// CHECK-LABEL: @test_mm_maskz_cvtepi32_ps
// CHECK: @llvm.x86.sse2.cvtdq2ps
// CHECK: sitofp <4 x i32> %{{.*}} to <4 x float>
// CHECK: select <4 x i1> {{.*}}, <4 x float> {{.*}}, <4 x float> {{.*}}
return _mm_maskz_cvtepi32_ps(__U,__A);
}
__m256 test_mm256_mask_cvtepi32_ps(__m256 __W, __mmask8 __U, __m256i __A) {
// CHECK-LABEL: @test_mm256_mask_cvtepi32_ps
// CHECK: @llvm.x86.avx.cvtdq2.ps.256
// CHECK: sitofp <8 x i32> %{{.*}} to <8 x float>
// CHECK: select <8 x i1> {{.*}}, <8 x float> {{.*}}, <8 x float> {{.*}}
return _mm256_mask_cvtepi32_ps(__W,__U,__A);
}
__m256 test_mm256_maskz_cvtepi32_ps(__mmask16 __U, __m256i __A) {
// CHECK-LABEL: @test_mm256_maskz_cvtepi32_ps
// CHECK: @llvm.x86.avx.cvtdq2.ps.256
// CHECK: sitofp <8 x i32> %{{.*}} to <8 x float>
// CHECK: select <8 x i1> {{.*}}, <8 x float> {{.*}}, <8 x float> {{.*}}
return _mm256_maskz_cvtepi32_ps(__U,__A);
}
@ -2110,32 +2110,36 @@ __m256d test_mm256_maskz_cvtepu32_pd(__mmask8 __U, __m128i __A) {
}
__m128 test_mm_cvtepu32_ps(__m128i __A) {
// CHECK-LABEL: @test_mm_cvtepu32_ps
// CHECK: @llvm.x86.avx512.mask.cvtudq2ps.128
// CHECK: uitofp <4 x i32> %{{.*}} to <4 x float>
return _mm_cvtepu32_ps(__A);
}
__m128 test_mm_mask_cvtepu32_ps(__m128 __W, __mmask8 __U, __m128i __A) {
// CHECK-LABEL: @test_mm_mask_cvtepu32_ps
// CHECK: @llvm.x86.avx512.mask.cvtudq2ps.128
// CHECK: uitofp <4 x i32> %{{.*}} to <4 x float>
// CHECK: select <4 x i1> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}
return _mm_mask_cvtepu32_ps(__W,__U,__A);
}
__m128 test_mm_maskz_cvtepu32_ps(__mmask8 __U, __m128i __A) {
// CHECK-LABEL: @test_mm_maskz_cvtepu32_ps
// CHECK: @llvm.x86.avx512.mask.cvtudq2ps.128
// CHECK: uitofp <4 x i32> %{{.*}} to <4 x float>
// CHECK: select <4 x i1> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}
return _mm_maskz_cvtepu32_ps(__U,__A);
}
__m256 test_mm256_cvtepu32_ps(__m256i __A) {
// CHECK-LABEL: @test_mm256_cvtepu32_ps
// CHECK: @llvm.x86.avx512.mask.cvtudq2ps.256
// CHECK: uitofp <8 x i32> %{{.*}} to <8 x float>
return _mm256_cvtepu32_ps(__A);
}
__m256 test_mm256_mask_cvtepu32_ps(__m256 __W, __mmask8 __U, __m256i __A) {
// CHECK-LABEL: @test_mm256_mask_cvtepu32_ps
// CHECK: @llvm.x86.avx512.mask.cvtudq2ps.256
// CHECK: uitofp <8 x i32> %{{.*}} to <8 x float>
// CHECK: select <8 x i1> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}
return _mm256_mask_cvtepu32_ps(__W,__U,__A);
}
__m256 test_mm256_maskz_cvtepu32_ps(__mmask8 __U, __m256i __A) {
// CHECK-LABEL: @test_mm256_maskz_cvtepu32_ps
// CHECK: @llvm.x86.avx512.mask.cvtudq2ps.256
// CHECK: uitofp <8 x i32> %{{.*}} to <8 x float>
// CHECK: select <8 x i1> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}
return _mm256_maskz_cvtepu32_ps(__U,__A);
}
__m128d test_mm_mask_div_pd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {

View File

@ -421,37 +421,41 @@ __m256i test_mm256_maskz_cvtps_epu64(__mmask8 __U, __m128 __A) {
__m128d test_mm_cvtepi64_pd(__m128i __A) {
// CHECK-LABEL: @test_mm_cvtepi64_pd
// CHECK: @llvm.x86.avx512.mask.cvtqq2pd.128
// CHECK: sitofp <2 x i64> %{{.*}} to <2 x double>
return _mm_cvtepi64_pd(__A);
}
__m128d test_mm_mask_cvtepi64_pd(__m128d __W, __mmask8 __U, __m128i __A) {
// CHECK-LABEL: @test_mm_mask_cvtepi64_pd
// CHECK: @llvm.x86.avx512.mask.cvtqq2pd.128
// CHECK: sitofp <2 x i64> %{{.*}} to <2 x double>
// CHECK: select <2 x i1> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}
return _mm_mask_cvtepi64_pd(__W, __U, __A);
}
__m128d test_mm_maskz_cvtepi64_pd(__mmask8 __U, __m128i __A) {
// CHECK-LABEL: @test_mm_maskz_cvtepi64_pd
// CHECK: @llvm.x86.avx512.mask.cvtqq2pd.128
// CHECK: sitofp <2 x i64> %{{.*}} to <2 x double>
// CHECK: select <2 x i1> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}
return _mm_maskz_cvtepi64_pd(__U, __A);
}
__m256d test_mm256_cvtepi64_pd(__m256i __A) {
// CHECK-LABEL: @test_mm256_cvtepi64_pd
// CHECK: @llvm.x86.avx512.mask.cvtqq2pd.256
// CHECK: sitofp <4 x i64> %{{.*}} to <4 x double>
return _mm256_cvtepi64_pd(__A);
}
__m256d test_mm256_mask_cvtepi64_pd(__m256d __W, __mmask8 __U, __m256i __A) {
// CHECK-LABEL: @test_mm256_mask_cvtepi64_pd
// CHECK: @llvm.x86.avx512.mask.cvtqq2pd.256
// CHECK: sitofp <4 x i64> %{{.*}} to <4 x double>
// CHECK: select <4 x i1> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}
return _mm256_mask_cvtepi64_pd(__W, __U, __A);
}
__m256d test_mm256_maskz_cvtepi64_pd(__mmask8 __U, __m256i __A) {
// CHECK-LABEL: @test_mm256_maskz_cvtepi64_pd
// CHECK: @llvm.x86.avx512.mask.cvtqq2pd.256
// CHECK: sitofp <4 x i64> %{{.*}} to <4 x double>
// CHECK: select <4 x i1> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}
return _mm256_maskz_cvtepi64_pd(__U, __A);
}
@ -637,37 +641,41 @@ __m256i test_mm256_maskz_cvttps_epu64(__mmask8 __U, __m128 __A) {
__m128d test_mm_cvtepu64_pd(__m128i __A) {
// CHECK-LABEL: @test_mm_cvtepu64_pd
// CHECK: @llvm.x86.avx512.mask.cvtuqq2pd.128
// CHECK: uitofp <2 x i64> %{{.*}} to <2 x double>
return _mm_cvtepu64_pd(__A);
}
__m128d test_mm_mask_cvtepu64_pd(__m128d __W, __mmask8 __U, __m128i __A) {
// CHECK-LABEL: @test_mm_mask_cvtepu64_pd
// CHECK: @llvm.x86.avx512.mask.cvtuqq2pd.128
// CHECK: uitofp <2 x i64> %{{.*}} to <2 x double>
// CHECK: select <2 x i1> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}
return _mm_mask_cvtepu64_pd(__W, __U, __A);
}
__m128d test_mm_maskz_cvtepu64_pd(__mmask8 __U, __m128i __A) {
// CHECK-LABEL: @test_mm_maskz_cvtepu64_pd
// CHECK: @llvm.x86.avx512.mask.cvtuqq2pd.128
// CHECK: uitofp <2 x i64> %{{.*}} to <2 x double>
// CHECK: select <2 x i1> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}}
return _mm_maskz_cvtepu64_pd(__U, __A);
}
__m256d test_mm256_cvtepu64_pd(__m256i __A) {
// CHECK-LABEL: @test_mm256_cvtepu64_pd
// CHECK: @llvm.x86.avx512.mask.cvtuqq2pd.256
// CHECK: uitofp <4 x i64> %{{.*}} to <4 x double>
return _mm256_cvtepu64_pd(__A);
}
__m256d test_mm256_mask_cvtepu64_pd(__m256d __W, __mmask8 __U, __m256i __A) {
// CHECK-LABEL: @test_mm256_mask_cvtepu64_pd
// CHECK: @llvm.x86.avx512.mask.cvtuqq2pd.256
// CHECK: uitofp <4 x i64> %{{.*}} to <4 x double>
// CHECK: select <4 x i1> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}
return _mm256_mask_cvtepu64_pd(__W, __U, __A);
}
__m256d test_mm256_maskz_cvtepu64_pd(__mmask8 __U, __m256i __A) {
// CHECK-LABEL: @test_mm256_maskz_cvtepu64_pd
// CHECK: @llvm.x86.avx512.mask.cvtuqq2pd.256
// CHECK: uitofp <4 x i64> %{{.*}} to <4 x double>
// CHECK: select <4 x i1> %{{.*}}, <4 x double> %{{.*}}, <4 x double> %{{.*}}
return _mm256_maskz_cvtepu64_pd(__U, __A);
}

View File

@ -338,7 +338,6 @@ void f0() {
tmp_V2LLi = __builtin_ia32_psadbw128(tmp_V16c, tmp_V16c);
tmp_V2d = __builtin_ia32_sqrtpd(tmp_V2d);
tmp_V2d = __builtin_ia32_sqrtsd(tmp_V2d);
tmp_V4f = __builtin_ia32_cvtdq2ps(tmp_V4i);
tmp_V2LLi = __builtin_ia32_cvtpd2dq(tmp_V2d);
tmp_V2i = __builtin_ia32_cvtpd2pi(tmp_V2d);
tmp_V4f = __builtin_ia32_cvtpd2ps(tmp_V2d);

View File

@ -468,7 +468,7 @@ __m128d test_mm_cvtepi32_pd(__m128i A) {
__m128 test_mm_cvtepi32_ps(__m128i A) {
// CHECK-LABEL: test_mm_cvtepi32_ps
// CHECK: call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %{{.*}})
// CHECK: sitofp <4 x i32> %{{.*}} to <4 x float>
return _mm_cvtepi32_ps(A);
}