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https://github.com/capstone-engine/llvm-capstone.git
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[AMDGPU] Do not widen scalar loads on GFX12 (#78724)
GFX12 has subword scalar loads so there is no need to do this.
This commit is contained in:
Jay Foad
GitHub
parent
aac1d9710b
commit
89226ecbb9
@ -13,9 +13,11 @@
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUTargetMachine.h"
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#include "llvm/Analysis/AssumptionCache.h"
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#include "llvm/Analysis/UniformityAnalysis.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/InstVisitor.h"
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#include "llvm/InitializePasses.h"
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@ -58,6 +60,7 @@ public:
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<TargetPassConfig>();
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AU.addRequired<AssumptionCacheTracker>();
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AU.addRequired<UniformityInfoWrapperPass>();
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AU.setPreservesAll();
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@ -90,7 +93,11 @@ bool AMDGPULateCodeGenPrepare::runOnFunction(Function &F) {
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if (skipFunction(F))
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return false;
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// TODO: Skip this on GFX12 which does have scalar sub-dword loads.
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const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
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const TargetMachine &TM = TPC.getTM<TargetMachine>();
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const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
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if (ST.hasScalarSubwordLoads())
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return false;
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AC = &getAnalysis<AssumptionCacheTracker>().getAssumptionCache(F);
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UA = &getAnalysis<UniformityInfoWrapperPass>().getUniformityInfo();
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@ -181,6 +188,7 @@ bool AMDGPULateCodeGenPrepare::visitLoadInst(LoadInst &LI) {
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INITIALIZE_PASS_BEGIN(AMDGPULateCodeGenPrepare, DEBUG_TYPE,
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"AMDGPU IR late optimizations", false, false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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INITIALIZE_PASS_DEPENDENCY(AssumptionCacheTracker)
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INITIALIZE_PASS_DEPENDENCY(UniformityInfoWrapperPass)
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INITIALIZE_PASS_END(AMDGPULateCodeGenPrepare, DEBUG_TYPE,
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@ -1,15 +1,21 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-late-codegenprepare %s | FileCheck %s
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-late-codegenprepare %s | FileCheck %s -check-prefix=GFX9
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -amdgpu-late-codegenprepare %s | FileCheck %s -check-prefix=GFX12
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; Make sure we don't crash when trying to create a bitcast between
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; address spaces
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define amdgpu_kernel void @constant_from_offset_cast_generic_null() {
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; CHECK-LABEL: @constant_from_offset_cast_generic_null(
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(4) getelementptr (i8, ptr addrspace(4) addrspacecast (ptr null to ptr addrspace(4)), i64 4), align 4
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; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 16
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; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
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; CHECK-NEXT: store i8 [[TMP3]], ptr addrspace(1) undef, align 1
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; CHECK-NEXT: ret void
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; GFX9-LABEL: @constant_from_offset_cast_generic_null(
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; GFX9-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(4) getelementptr (i8, ptr addrspace(4) addrspacecast (ptr null to ptr addrspace(4)), i64 4), align 4
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; GFX9-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 16
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; GFX9-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
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; GFX9-NEXT: store i8 [[TMP3]], ptr addrspace(1) undef, align 1
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; GFX9-NEXT: ret void
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;
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; GFX12-LABEL: @constant_from_offset_cast_generic_null(
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; GFX12-NEXT: [[LOAD:%.*]] = load i8, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) addrspacecast (ptr null to ptr addrspace(4)), i64 6), align 1
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; GFX12-NEXT: store i8 [[LOAD]], ptr addrspace(1) undef, align 1
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; GFX12-NEXT: ret void
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;
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%load = load i8, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) addrspacecast (ptr null to ptr addrspace(4)), i64 6), align 1
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store i8 %load, ptr addrspace(1) undef
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@ -17,12 +23,17 @@ define amdgpu_kernel void @constant_from_offset_cast_generic_null() {
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}
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define amdgpu_kernel void @constant_from_offset_cast_global_null() {
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; CHECK-LABEL: @constant_from_offset_cast_global_null(
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(4) getelementptr (i8, ptr addrspace(4) addrspacecast (ptr addrspace(1) null to ptr addrspace(4)), i64 4), align 4
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; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 16
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; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
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; CHECK-NEXT: store i8 [[TMP3]], ptr addrspace(1) undef, align 1
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; CHECK-NEXT: ret void
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; GFX9-LABEL: @constant_from_offset_cast_global_null(
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; GFX9-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(4) getelementptr (i8, ptr addrspace(4) addrspacecast (ptr addrspace(1) null to ptr addrspace(4)), i64 4), align 4
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; GFX9-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 16
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; GFX9-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
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; GFX9-NEXT: store i8 [[TMP3]], ptr addrspace(1) undef, align 1
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; GFX9-NEXT: ret void
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;
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; GFX12-LABEL: @constant_from_offset_cast_global_null(
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; GFX12-NEXT: [[LOAD:%.*]] = load i8, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) addrspacecast (ptr addrspace(1) null to ptr addrspace(4)), i64 6), align 1
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; GFX12-NEXT: store i8 [[LOAD]], ptr addrspace(1) undef, align 1
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; GFX12-NEXT: ret void
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;
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%load = load i8, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) addrspacecast (ptr addrspace(1) null to ptr addrspace(4)), i64 6), align 1
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store i8 %load, ptr addrspace(1) undef
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@ -32,12 +43,17 @@ define amdgpu_kernel void @constant_from_offset_cast_global_null() {
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@gv = unnamed_addr addrspace(1) global [64 x i8] undef, align 4
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define amdgpu_kernel void @constant_from_offset_cast_global_gv() {
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; CHECK-LABEL: @constant_from_offset_cast_global_gv(
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(4) getelementptr (i8, ptr addrspace(4) addrspacecast (ptr addrspace(1) @gv to ptr addrspace(4)), i64 4), align 4
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; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 16
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; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
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; CHECK-NEXT: store i8 [[TMP3]], ptr addrspace(1) undef, align 1
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; CHECK-NEXT: ret void
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; GFX9-LABEL: @constant_from_offset_cast_global_gv(
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; GFX9-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(4) getelementptr (i8, ptr addrspace(4) addrspacecast (ptr addrspace(1) @gv to ptr addrspace(4)), i64 4), align 4
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; GFX9-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 16
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; GFX9-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
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; GFX9-NEXT: store i8 [[TMP3]], ptr addrspace(1) undef, align 1
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; GFX9-NEXT: ret void
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;
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; GFX12-LABEL: @constant_from_offset_cast_global_gv(
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; GFX12-NEXT: [[LOAD:%.*]] = load i8, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) addrspacecast (ptr addrspace(1) @gv to ptr addrspace(4)), i64 6), align 1
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; GFX12-NEXT: store i8 [[LOAD]], ptr addrspace(1) undef, align 1
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; GFX12-NEXT: ret void
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;
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%load = load i8, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) addrspacecast (ptr addrspace(1) @gv to ptr addrspace(4)), i64 6), align 1
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store i8 %load, ptr addrspace(1) undef
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@ -45,12 +61,17 @@ define amdgpu_kernel void @constant_from_offset_cast_global_gv() {
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}
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define amdgpu_kernel void @constant_from_offset_cast_generic_inttoptr() {
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; CHECK-LABEL: @constant_from_offset_cast_generic_inttoptr(
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(4) getelementptr (i8, ptr addrspace(4) addrspacecast (ptr inttoptr (i64 128 to ptr) to ptr addrspace(4)), i64 4), align 4
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; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 16
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; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
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; CHECK-NEXT: store i8 [[TMP3]], ptr addrspace(1) undef, align 1
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; CHECK-NEXT: ret void
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; GFX9-LABEL: @constant_from_offset_cast_generic_inttoptr(
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; GFX9-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(4) getelementptr (i8, ptr addrspace(4) addrspacecast (ptr inttoptr (i64 128 to ptr) to ptr addrspace(4)), i64 4), align 4
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; GFX9-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 16
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; GFX9-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8
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; GFX9-NEXT: store i8 [[TMP3]], ptr addrspace(1) undef, align 1
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; GFX9-NEXT: ret void
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;
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; GFX12-LABEL: @constant_from_offset_cast_generic_inttoptr(
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; GFX12-NEXT: [[LOAD:%.*]] = load i8, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) addrspacecast (ptr inttoptr (i64 128 to ptr) to ptr addrspace(4)), i64 6), align 1
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; GFX12-NEXT: store i8 [[LOAD]], ptr addrspace(1) undef, align 1
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; GFX12-NEXT: ret void
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;
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%load = load i8, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) addrspacecast (ptr inttoptr (i64 128 to ptr) to ptr addrspace(4)), i64 6), align 1
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store i8 %load, ptr addrspace(1) undef
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@ -58,10 +79,15 @@ define amdgpu_kernel void @constant_from_offset_cast_generic_inttoptr() {
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}
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define amdgpu_kernel void @constant_from_inttoptr() {
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; CHECK-LABEL: @constant_from_inttoptr(
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; CHECK-NEXT: [[LOAD:%.*]] = load i8, ptr addrspace(4) inttoptr (i64 128 to ptr addrspace(4)), align 4
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; CHECK-NEXT: store i8 [[LOAD]], ptr addrspace(1) undef, align 1
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; CHECK-NEXT: ret void
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; GFX9-LABEL: @constant_from_inttoptr(
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; GFX9-NEXT: [[LOAD:%.*]] = load i8, ptr addrspace(4) inttoptr (i64 128 to ptr addrspace(4)), align 4
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; GFX9-NEXT: store i8 [[LOAD]], ptr addrspace(1) undef, align 1
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; GFX9-NEXT: ret void
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;
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; GFX12-LABEL: @constant_from_inttoptr(
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; GFX12-NEXT: [[LOAD:%.*]] = load i8, ptr addrspace(4) inttoptr (i64 128 to ptr addrspace(4)), align 1
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; GFX12-NEXT: store i8 [[LOAD]], ptr addrspace(1) undef, align 1
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; GFX12-NEXT: ret void
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;
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%load = load i8, ptr addrspace(4) inttoptr (i64 128 to ptr addrspace(4)), align 1
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store i8 %load, ptr addrspace(1) undef
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@ -1,5 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s -check-prefix=GFX9
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck %s -check-prefix=GFX12
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; We have an indirect call with a known set of callees, which are
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; known to not need any special inputs. The ABI still needs to use the
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@ -8,35 +9,63 @@
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; FIXME: Passing real values for workitem ID, and 0s that can be undef
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define amdgpu_kernel void @indirect_call_known_no_special_inputs() {
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; CHECK-LABEL: indirect_call_known_no_special_inputs:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_add_u32 flat_scratch_lo, s4, s7
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; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
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; CHECK-NEXT: s_add_u32 s0, s0, s7
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; CHECK-NEXT: s_addc_u32 s1, s1, 0
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; CHECK-NEXT: s_mov_b64 s[4:5], 0
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; CHECK-NEXT: s_load_dword s7, s[4:5], 0x0
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; CHECK-NEXT: s_getpc_b64 s[4:5]
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; CHECK-NEXT: s_add_u32 s4, s4, wobble@gotpcrel32@lo+4
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; CHECK-NEXT: s_addc_u32 s5, s5, wobble@gotpcrel32@hi+12
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; CHECK-NEXT: s_getpc_b64 s[8:9]
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; CHECK-NEXT: s_add_u32 s8, s8, snork@gotpcrel32@lo+4
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; CHECK-NEXT: s_addc_u32 s9, s9, snork@gotpcrel32@hi+12
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; CHECK-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x0
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; CHECK-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x0
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; CHECK-NEXT: s_mov_b64 s[8:9], 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_and_b32 s4, 1, s7
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; CHECK-NEXT: s_cmp_eq_u32 s4, 1
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; CHECK-NEXT: v_mov_b32_e32 v31, v0
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; CHECK-NEXT: s_cselect_b32 s5, s13, s11
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; CHECK-NEXT: s_cselect_b32 s4, s12, s10
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; CHECK-NEXT: s_mov_b32 s12, s6
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; CHECK-NEXT: v_mov_b32_e32 v1, 0
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; CHECK-NEXT: v_mov_b32_e32 v4, 0
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; CHECK-NEXT: s_mov_b32 s32, 0
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; CHECK-NEXT: s_endpgm
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; GFX9-LABEL: indirect_call_known_no_special_inputs:
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; GFX9: ; %bb.0: ; %bb
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; GFX9-NEXT: s_add_u32 flat_scratch_lo, s4, s7
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; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
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; GFX9-NEXT: s_add_u32 s0, s0, s7
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; GFX9-NEXT: s_addc_u32 s1, s1, 0
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; GFX9-NEXT: s_mov_b64 s[4:5], 0
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; GFX9-NEXT: s_load_dword s7, s[4:5], 0x0
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; GFX9-NEXT: s_getpc_b64 s[4:5]
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; GFX9-NEXT: s_add_u32 s4, s4, wobble@gotpcrel32@lo+4
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; GFX9-NEXT: s_addc_u32 s5, s5, wobble@gotpcrel32@hi+12
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; GFX9-NEXT: s_getpc_b64 s[8:9]
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; GFX9-NEXT: s_add_u32 s8, s8, snork@gotpcrel32@lo+4
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; GFX9-NEXT: s_addc_u32 s9, s9, snork@gotpcrel32@hi+12
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; GFX9-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x0
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; GFX9-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x0
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; GFX9-NEXT: s_mov_b64 s[8:9], 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_and_b32 s4, 1, s7
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; GFX9-NEXT: s_cmp_eq_u32 s4, 1
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; GFX9-NEXT: v_mov_b32_e32 v31, v0
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; GFX9-NEXT: s_cselect_b32 s5, s13, s11
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; GFX9-NEXT: s_cselect_b32 s4, s12, s10
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; GFX9-NEXT: s_mov_b32 s12, s6
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; GFX9-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-NEXT: v_mov_b32_e32 v4, 0
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; GFX9-NEXT: s_mov_b32 s32, 0
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; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GFX9-NEXT: s_endpgm
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;
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; GFX12-LABEL: indirect_call_known_no_special_inputs:
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; GFX12: ; %bb.0: ; %bb
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; GFX12-NEXT: s_getpc_b64 s[4:5]
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; GFX12-NEXT: s_sext_i32_i16 s5, s5
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; GFX12-NEXT: s_add_co_u32 s4, s4, snork@gotpcrel32@lo+8
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; GFX12-NEXT: s_add_co_ci_u32 s5, s5, snork@gotpcrel32@hi+16
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; GFX12-NEXT: s_mov_b64 s[2:3], 0
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; GFX12-NEXT: s_getpc_b64 s[6:7]
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; GFX12-NEXT: s_sext_i32_i16 s7, s7
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; GFX12-NEXT: s_add_co_u32 s6, s6, wobble@gotpcrel32@lo+8
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; GFX12-NEXT: s_add_co_ci_u32 s7, s7, wobble@gotpcrel32@hi+16
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; GFX12-NEXT: s_load_u8 s1, s[2:3], 0x0
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; GFX12-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
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; GFX12-NEXT: s_load_b64 s[4:5], s[6:7], 0x0
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; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
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; GFX12-NEXT: v_mov_b32_e32 v31, v0
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; GFX12-NEXT: s_mov_b64 s[8:9], 0
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; GFX12-NEXT: s_mov_b32 s12, s0
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; GFX12-NEXT: s_mov_b32 s32, 0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_and_b32 s1, 1, s1
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
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; GFX12-NEXT: s_cmp_eq_u32 s1, 1
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; GFX12-NEXT: s_cselect_b32 s3, s5, s3
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; GFX12-NEXT: s_cselect_b32 s2, s4, s2
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; GFX12-NEXT: s_swappc_b64 s[30:31], s[2:3]
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; GFX12-NEXT: s_endpgm
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bb:
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%cond = load i1, ptr addrspace(4) null
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@ -46,19 +75,37 @@ bb:
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}
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define void @wobble() {
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; CHECK-LABEL: wobble:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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; GFX9-LABEL: wobble:
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; GFX9: ; %bb.0: ; %bb
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
|
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; GFX12-LABEL: wobble:
|
||||
; GFX12: ; %bb.0: ; %bb
|
||||
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
; GFX12-NEXT: s_wait_expcnt 0x0
|
||||
; GFX12-NEXT: s_wait_samplecnt 0x0
|
||||
; GFX12-NEXT: s_wait_bvhcnt 0x0
|
||||
; GFX12-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-NEXT: s_setpc_b64 s[30:31]
|
||||
bb:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @snork() {
|
||||
; CHECK-LABEL: snork:
|
||||
; CHECK: ; %bb.0: ; %bb
|
||||
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; CHECK-NEXT: s_setpc_b64 s[30:31]
|
||||
; GFX9-LABEL: snork:
|
||||
; GFX9: ; %bb.0: ; %bb
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GFX12-LABEL: snork:
|
||||
; GFX12: ; %bb.0: ; %bb
|
||||
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
|
||||
; GFX12-NEXT: s_wait_expcnt 0x0
|
||||
; GFX12-NEXT: s_wait_samplecnt 0x0
|
||||
; GFX12-NEXT: s_wait_bvhcnt 0x0
|
||||
; GFX12-NEXT: s_wait_kmcnt 0x0
|
||||
; GFX12-NEXT: s_setpc_b64 s[30:31]
|
||||
bb:
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user