From 89ca4eb002021b7e11037a5577e2ee9bc570be42 Mon Sep 17 00:00:00 2001 From: Shengchen Kan Date: Sat, 20 May 2023 11:30:28 +0800 Subject: [PATCH] [X86][NFC] Correct the instruction names for PUSH16i, PUSH32i Reviewed By: maksfb Differential Revision: https://reviews.llvm.org/D151012 --- bolt/lib/Target/X86/X86MCPlusBuilder.cpp | 8 ++++---- llvm/lib/Target/X86/MCTargetDesc/X86InstrRelaxTables.cpp | 4 ++-- llvm/lib/Target/X86/X86CallFrameOptimization.cpp | 2 +- llvm/lib/Target/X86/X86DynAllocaExpander.cpp | 2 +- llvm/lib/Target/X86/X86FrameLowering.cpp | 4 ++-- llvm/lib/Target/X86/X86InstrInfo.cpp | 2 +- llvm/lib/Target/X86/X86InstrMisc.td | 4 ++-- llvm/lib/Target/X86/X86ScheduleAtom.td | 2 +- 8 files changed, 14 insertions(+), 14 deletions(-) diff --git a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp index 6c9b5e188fd7..a1a86e9c13d8 100644 --- a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp +++ b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp @@ -270,7 +270,7 @@ public: case X86::PUSHFS16: case X86::PUSHGS16: case X86::PUSHSS16: - case X86::PUSHi16: + case X86::PUSH16i: return 2; case X86::PUSH32i8: case X86::PUSH32r: @@ -284,7 +284,7 @@ public: case X86::PUSHFS32: case X86::PUSHGS32: case X86::PUSHSS32: - case X86::PUSHi32: + case X86::PUSH32i: return 4; case X86::PUSH64i32: case X86::PUSH64i8: @@ -2548,8 +2548,8 @@ public: default: { switch (getPushSize(Inst)) { - case 2: I = {2, false, {{CHECK8, X86::PUSH16i8}, {NOCHECK, X86::PUSHi16}}}; break; - case 4: I = {4, false, {{CHECK8, X86::PUSH32i8}, {NOCHECK, X86::PUSHi32}}}; break; + case 2: I = {2, false, {{CHECK8, X86::PUSH16i8}, {NOCHECK, X86::PUSH16i}}}; break; + case 4: I = {4, false, {{CHECK8, X86::PUSH32i8}, {NOCHECK, X86::PUSH32i}}}; break; case 8: I = {8, false, {{CHECK8, X86::PUSH64i8}, {CHECK32, X86::PUSH64i32}, {NOCHECK, Inst.getOpcode()}}}; break; diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstrRelaxTables.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstrRelaxTables.cpp index 640efd468135..afeaaecfb5e0 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86InstrRelaxTables.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstrRelaxTables.cpp @@ -65,8 +65,8 @@ static const X86InstrRelaxTableEntry InstrRelaxTable[] = { { X86::OR64mi8, X86::OR64mi32 }, { X86::OR64ri8, X86::OR64ri32 }, // PUSH - { X86::PUSH16i8, X86::PUSHi16 }, - { X86::PUSH32i8, X86::PUSHi32 }, + { X86::PUSH16i8, X86::PUSH16i }, + { X86::PUSH32i8, X86::PUSH32i }, { X86::PUSH64i8, X86::PUSH64i32 }, // SBB { X86::SBB16mi8, X86::SBB16mi }, diff --git a/llvm/lib/Target/X86/X86CallFrameOptimization.cpp b/llvm/lib/Target/X86/X86CallFrameOptimization.cpp index 1367d2e3d2ba..2bebd013a878 100644 --- a/llvm/lib/Target/X86/X86CallFrameOptimization.cpp +++ b/llvm/lib/Target/X86/X86CallFrameOptimization.cpp @@ -520,7 +520,7 @@ void X86CallFrameOptimization::adjustCallSequence(MachineFunction &MF, case X86::OR64mi32: case X86::MOV32mi: case X86::MOV64mi32: - PushOpcode = Is64Bit ? X86::PUSH64i32 : X86::PUSHi32; + PushOpcode = Is64Bit ? X86::PUSH64i32 : X86::PUSH32i; // If the operand is a small (8-bit) immediate, we can use a // PUSH instruction with a shorter encoding. // Note that isImm() may fail even though this is a MOVmi, because diff --git a/llvm/lib/Target/X86/X86DynAllocaExpander.cpp b/llvm/lib/Target/X86/X86DynAllocaExpander.cpp index bd2a663f893a..978f2db8f017 100644 --- a/llvm/lib/Target/X86/X86DynAllocaExpander.cpp +++ b/llvm/lib/Target/X86/X86DynAllocaExpander.cpp @@ -114,7 +114,7 @@ static bool isPushPop(const MachineInstr &MI) { case X86::PUSH32r: case X86::PUSH32rmm: case X86::PUSH32rmr: - case X86::PUSHi32: + case X86::PUSH32i: case X86::PUSH64i8: case X86::PUSH64r: case X86::PUSH64rmm: diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp index fed7131b0299..0619029aeae8 100644 --- a/llvm/lib/Target/X86/X86FrameLowering.cpp +++ b/llvm/lib/Target/X86/X86FrameLowering.cpp @@ -3251,9 +3251,9 @@ void X86FrameLowering::adjustForSegmentedStacks( Reg11) .addImm(X86FI->getArgumentStackSize()); } else { - BuildMI(allocMBB, DL, TII.get(X86::PUSHi32)) + BuildMI(allocMBB, DL, TII.get(X86::PUSH32i)) .addImm(X86FI->getArgumentStackSize()); - BuildMI(allocMBB, DL, TII.get(X86::PUSHi32)) + BuildMI(allocMBB, DL, TII.get(X86::PUSH32i)) .addImm(StackSize); } diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 708943fd9da1..6c1bc59d0239 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -436,7 +436,7 @@ int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const { case X86::PUSH32r: case X86::PUSH32rmm: case X86::PUSH32rmr: - case X86::PUSHi32: + case X86::PUSH32i: return 4; case X86::PUSH64i8: case X86::PUSH64r: diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index f3ca5bc5d0b5..88e7a388713f 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -92,13 +92,13 @@ def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), "push{w}\t$imm", []>, OpSize16; -def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), +def PUSH16i : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), "push{w}\t$imm", []>, OpSize16; def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), "push{l}\t$imm", []>, OpSize32, Requires<[Not64BitMode]>; -def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), +def PUSH32i : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), "push{l}\t$imm", []>, OpSize32, Requires<[Not64BitMode]>; } // mayStore, SchedRW diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td index 09a09185b3bc..b7336161b2e0 100644 --- a/llvm/lib/Target/X86/X86ScheduleAtom.td +++ b/llvm/lib/Target/X86/X86ScheduleAtom.td @@ -537,7 +537,7 @@ def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> { def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r, POP16rmr, POP32rmr, POP64rmr, PUSH16r, PUSH32r, PUSH64r, - PUSHi16, PUSHi32, + PUSH16i, PUSH32i, PUSH16rmr, PUSH32rmr, PUSH64rmr, PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32, XCH_F)>;