Magic-Mirror/llvm-capstone
1
0
Fork 0
mirror of https://github.com/capstone-engine/llvm-capstone.git synced 2024-12-14 03:29:57 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Fix SelectionDAGBuild lowering of Select instructions to

Browse Source 
handle first-class aggregate values. Also, fix a bug in
the Ret handling for empty aggregates.

llvm-svn: 57925
This commit is contained in:
Dan Gohman 2008-10-21 20:00:42 +00:00
parent 30c514e763
commit 8b44b88eff
2 changed files with 46 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
View File

@ -902,11 +902,13 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) {
SmallVector<SDValue, 8> NewValues;
NewValues.push_back(getControlRoot());
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
SDValue RetOp = getValue(I.getOperand(i));
SmallVector<MVT, 4> ValueVTs;
ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
for (unsigned j = 0, f = ValueVTs.size(); j != f; ++j) {
unsigned NumValues = ValueVTs.size();
if (NumValues == 0) continue;
SDValue RetOp = getValue(I.getOperand(i));
for (unsigned j = 0, f = NumValues; j != f; ++j) {
MVT VT = ValueVTs[j];
// FIXME: C calling convention requires the return type to be promoted to
@ -2137,11 +2139,23 @@ void SelectionDAGLowering::visitVFCmp(User &I) {
}
void SelectionDAGLowering::visitSelect(User &I) {
SDValue Cond = getValue(I.getOperand(0));
SDValue TrueVal = getValue(I.getOperand(1));
SDValue FalseVal = getValue(I.getOperand(2));
setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
TrueVal, FalseVal));
SmallVector<MVT, 4> ValueVTs;
ComputeValueVTs(TLI, I.getType(), ValueVTs);
unsigned NumValues = ValueVTs.size();
if (NumValues != 0) {
SmallVector<SDValue, 4> Values(NumValues);
SDValue Cond = getValue(I.getOperand(0));
SDValue TrueVal = getValue(I.getOperand(1));
SDValue FalseVal = getValue(I.getOperand(2));
for (unsigned i = 0; i != NumValues; ++i)
Values[i] = DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues),
&Values[0], NumValues));
}
}

24
llvm/test/CodeGen/X86/pr2924.ll Normal file
View File

@ -0,0 +1,24 @@
; RUN: llvm-as < %s | llc
; PR2924
target datalayout =
"e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i686-pc-linux-gnu"
define x86_stdcallcc { i32, i8* } @_D3std6string7toupperFAaZAa({ i32, i8* } %s) {
entry_std.string.toupper:
%tmp58 = load i32* null
%tmp59 = icmp eq i32 %tmp58, 0
%r.val = load { i32, i8* }* null, align 8
%condtmp.0 = select i1 %tmp59, { i32, i8* } undef, { i32, i8* } %r.val
ret { i32, i8* } %condtmp.0
}
define { } @empty({ } %s) {
entry_std.string.toupper:
%tmp58 = load i32* null
%tmp59 = icmp eq i32 %tmp58, 0
%r.val = load { }* null, align 8
%condtmp.0 = select i1 %tmp59, { } undef, { } %r.val
ret { } %condtmp.0
}