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Add missing closing brackets in PPC def files.

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Rot127 2024-03-12 01:25:32 -05:00 committed by Rot127
parent 5fd0c79cde
commit 8c89272eb9
2 changed files with 4 additions and 1 deletions
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2
llvm/lib/Target/PowerPC/PPCInstrInfo.td
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@ -4439,6 +4439,7 @@ def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST),
def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST),
(ins gprc:$RA, gprc:$RB),
"ldcix $RST, $RA, $RB", IIC_LdStLoad, []>;
} // mayLoad = 1
let mayStore = 1 in {
def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs),
@ -4453,6 +4454,7 @@ def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs),
def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs),
(ins gprc:$RST, gprc:$RA, gprc:$RB),
"stdcix $RST, $RA, $RB", IIC_LdStLoad, []>;
} // mayStore = 1
// External PID Load Store Instructions

3
llvm/lib/Target/PowerPC/PPCInstrSPE.td
View File

@ -806,6 +806,7 @@ def SPELWZ : DForm_1<32, (outs spe4rc:$RST), (ins (memri $D, $RA):$addr),
def SPELWZX : XForm_1<31, 23, (outs spe4rc:$RST), (ins (memrr $RA, $RB):$addr),
"lwzx $RST, $addr", IIC_LdStLoad,
[(set f32:$RST, (load xaddr:$addr))]>;
} // mayLoad = 1
let mayStore = 1 in {
def SPESTW : DForm_1<36, (outs), (ins spe4rc:$RST, (memri $D, $RA):$addr),
@ -814,7 +815,7 @@ def SPESTW : DForm_1<36, (outs), (ins spe4rc:$RST, (memri $D, $RA):$addr)
def SPESTWX : XForm_8<31, 151, (outs), (ins spe4rc:$RST, (memrr $RA, $RB):$addr),
"stwx $RST, $addr", IIC_LdStStore,
[(store f32:$RST, xaddr:$addr)]>;
}
} // mayStore = 1
}
} // HasSPE