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[mlir][ArmSME] Add vector to tile intrinsics
Add support for following vector to tile (MOVA) intrinsics to ArmSME dialect: llvm.aarch64.sme.write.vert llvm.aarch64.sme.write.horiz Includes the definition of new type predicate 'ScalableVectorOfRankAndLengthAndType' in OpBase.td. Reviewed By: awarzynski, dcaballe Differential Revision: https://reviews.llvm.org/D157004
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Cullen Rhodes
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@ -14,6 +14,7 @@
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#ifndef ARMSME_OPS
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#define ARMSME_OPS
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include "mlir/IR/OpBase.td"
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include "mlir/Interfaces/SideEffectInterfaces.td"
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include "mlir/Dialect/LLVMIR/LLVMOpBase.td"
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include "mlir/Interfaces/InferTypeOpInterface.td"
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@ -61,6 +62,12 @@ def nxnxv2f64 : SMETileType<F64, [2, 2 ], "vector<[2]x[2]xf64>">;
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def SMETile : AnyTypeOf<[nxnxv16i8, nxnxv8i16, nxnxv4i32, nxnxv2i64, nxnxv1i128,
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nxnxv8f16, nxnxv8bf16, nxnxv4f32, nxnxv2f64]>;
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def SVEVector : ScalableVectorOfRankAndLengthAndType<
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[1], [16, 8, 4, 2, 1], [I8, I16, I32, I64, I128, F16, BF16, F32, F64]>;
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def SVEPredicate : ScalableVectorOfRankAndLengthAndType<
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[1], [16, 8, 4, 2, 1], [I1]>;
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// A type constraint that verifies the bitwidth of the scalar integer returned
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// from 'arm_sme.get_tile_id' matches the element bitwidth of a "virtual tile".
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def TileElementWidthMatchesTileID : TypesMatchWith<
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@ -496,6 +503,18 @@ def LLVM_aarch64_sme_str
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Arguments<(ins Arg<I32, "Index">,
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Arg<LLVM_AnyPointer, "Store address", [MemWrite]>)>;
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// Vector to tile
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class LLVM_aarch64_sme_write<string direction>
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: ArmSME_IntrOp<"write." # direction, /*overloadedOperands=*/[3],
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[AllShapesMatch<["pg", "vector"]>]>,
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Arguments<(ins Arg<I32, "Virtual tile ID">,
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Arg<I32, "Tile slice">,
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Arg<SVEPredicate, "Vector predicate">:$pg,
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Arg<SVEVector, "Vector operand">:$vector)>;
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def LLVM_aarch64_sme_write_horiz : LLVM_aarch64_sme_write<"horiz">;
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def LLVM_aarch64_sme_write_vert : LLVM_aarch64_sme_write<"vert">;
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def LLVM_aarch64_sme_za_enable : ArmSME_IntrOp<"za.enable">;
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def LLVM_aarch64_sme_za_disable : ArmSME_IntrOp<"za.disable">;
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@ -533,6 +533,19 @@ class ScalableVectorOfLengthAndType<list<int> allowedLengths,
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ScalableVectorOfLength<allowedLengths>.summary,
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"::mlir::VectorType">;
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// Any scalable vector where the rank is from the given `allowedRanks` list and
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// the number of elements is from the given `allowedLengths` list and the type
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// is from the given `allowedTypes` list
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class ScalableVectorOfRankAndLengthAndType<list<int> allowedRanks,
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list<int> allowedLengths,
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list<Type> allowedTypes> : AllOfType<
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[ScalableVectorOfRank<allowedRanks>, ScalableVectorOf<allowedTypes>,
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ScalableVectorOfLength<allowedLengths>],
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ScalableVectorOfRank<allowedRanks>.summary #
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ScalableVectorOf<allowedTypes>.summary #
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ScalableVectorOfLength<allowedLengths>.summary,
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"::mlir::VectorType">;
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def AnyVector : VectorOf<[AnyType]>;
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// Temporary vector type clone that allows gradual transition to 0-D vectors.
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def AnyVectorOfAnyRank : VectorOfAnyRankOf<[AnyType]>;
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12
mlir/test/Target/LLVMIR/arm-sme-invalid.mlir
Normal file
12
mlir/test/Target/LLVMIR/arm-sme-invalid.mlir
Normal file
@ -0,0 +1,12 @@
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// RUN: mlir-translate -verify-diagnostics -split-input-file -mlir-to-llvmir %s
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// Verify shape of predicate and vector must match
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llvm.func @arm_sme_vector_to_tile_invalid_types(%tileslice : i32,
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%nxv4i1 : vector<[4]xi1>,
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%nxv16i8 : vector<[16]xi8>) {
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%tile = llvm.mlir.constant(0 : index) : i32
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// expected-error @+1 {{failed to verify that all of {pg, vector} have same shape}}
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"arm_sme.intr.write.horiz"(%tile, %tileslice, %nxv4i1, %nxv16i8) :
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(i32, i32, vector<[4]xi1>, vector<[16]xi8>) -> ()
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llvm.return
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}
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@ -236,3 +236,101 @@ llvm.func @arm_sme_toggle_za() {
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"arm_sme.intr.za.disable"() : () -> ()
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llvm.return
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}
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// -----
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// CHECK-LABEL: @arm_sme_vector_to_tile_horiz
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llvm.func @arm_sme_vector_to_tile_horiz(%tileslice : i32,
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%nxv16i1 : vector<[16]xi1>,
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%nxv8i1 : vector<[8]xi1>,
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%nxv4i1 : vector<[4]xi1>,
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%nxv2i1 : vector<[2]xi1>,
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%nxv1i1 : vector<[1]xi1>,
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%nxv16i8 : vector<[16]xi8>,
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%nxv8i16 : vector<[8]xi16>,
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%nxv4i32 : vector<[4]xi32>,
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%nxv2i64 : vector<[2]xi64>,
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%nxv1i128 : vector<[1]xi128>,
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%nxv8f16 : vector<[8]xf16>,
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%nxv8bf16 : vector<[8]xbf16>,
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%nxv4f32 : vector<[4]xf32>,
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%nxv2f64 : vector<[2]xf64>) {
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%tile = llvm.mlir.constant(0 : index) : i32
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// CHECK: call void @llvm.aarch64.sme.write.horiz.nxv16i8
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"arm_sme.intr.write.horiz"(%tile, %tileslice, %nxv16i1, %nxv16i8) :
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(i32, i32, vector<[16]xi1>, vector<[16]xi8>) -> ()
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// CHECK: call void @llvm.aarch64.sme.write.horiz.nxv8i16
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"arm_sme.intr.write.horiz"(%tile, %tileslice, %nxv8i1, %nxv8i16) :
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(i32, i32, vector<[8]xi1>, vector<[8]xi16>) -> ()
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// CHECK: call void @llvm.aarch64.sme.write.horiz.nxv4i32
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"arm_sme.intr.write.horiz"(%tile, %tileslice, %nxv4i1, %nxv4i32) :
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(i32, i32, vector<[4]xi1>, vector<[4]xi32>) -> ()
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// CHECK: call void @llvm.aarch64.sme.write.horiz.nxv2i64
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"arm_sme.intr.write.horiz"(%tile, %tileslice, %nxv2i1, %nxv2i64) :
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(i32, i32, vector<[2]xi1>, vector<[2]xi64>) -> ()
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// CHECK: call void @llvm.aarch64.sme.write.horiz.nxv1i128
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"arm_sme.intr.write.horiz"(%tile, %tileslice, %nxv1i1, %nxv1i128) :
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(i32, i32, vector<[1]xi1>, vector<[1]xi128>) -> ()
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// CHECK: call void @llvm.aarch64.sme.write.horiz.nxv8f16
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"arm_sme.intr.write.horiz"(%tile, %tileslice, %nxv8i1, %nxv8f16) :
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(i32, i32, vector<[8]xi1>, vector<[8]xf16>) -> ()
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// CHECK: call void @llvm.aarch64.sme.write.horiz.nxv8bf16
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"arm_sme.intr.write.horiz"(%tile, %tileslice, %nxv8i1, %nxv8bf16) :
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(i32, i32, vector<[8]xi1>, vector<[8]xbf16>) -> ()
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// CHECK: call void @llvm.aarch64.sme.write.horiz.nxv4f32
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"arm_sme.intr.write.horiz"(%tile, %tileslice, %nxv4i1, %nxv4f32) :
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(i32, i32, vector<[4]xi1>, vector<[4]xf32>) -> ()
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// CHECK: call void @llvm.aarch64.sme.write.horiz.nxv2f64
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"arm_sme.intr.write.horiz"(%tile, %tileslice, %nxv2i1, %nxv2f64) :
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(i32, i32, vector<[2]xi1>, vector<[2]xf64>) -> ()
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llvm.return
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}
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// -----
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// CHECK-LABEL: @arm_sme_vector_to_tile_vert
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llvm.func @arm_sme_vector_to_tile_vert(%tileslice : i32,
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%nxv16i1 : vector<[16]xi1>,
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%nxv8i1 : vector<[8]xi1>,
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%nxv4i1 : vector<[4]xi1>,
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%nxv2i1 : vector<[2]xi1>,
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%nxv1i1 : vector<[1]xi1>,
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%nxv16i8 : vector<[16]xi8>,
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%nxv8i16 : vector<[8]xi16>,
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%nxv4i32 : vector<[4]xi32>,
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%nxv2i64 : vector<[2]xi64>,
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%nxv1i128 : vector<[1]xi128>,
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%nxv8f16 : vector<[8]xf16>,
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%nxv8bf16 : vector<[8]xbf16>,
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%nxv4f32 : vector<[4]xf32>,
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%nxv2f64 : vector<[2]xf64>) {
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%tile = llvm.mlir.constant(0 : index) : i32
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// CHECK: call void @llvm.aarch64.sme.write.vert.nxv16i8
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"arm_sme.intr.write.vert"(%tile, %tileslice, %nxv16i1, %nxv16i8) :
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(i32, i32, vector<[16]xi1>, vector<[16]xi8>) -> ()
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// CHECK: call void @llvm.aarch64.sme.write.vert.nxv8i16
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"arm_sme.intr.write.vert"(%tile, %tileslice, %nxv8i1, %nxv8i16) :
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(i32, i32, vector<[8]xi1>, vector<[8]xi16>) -> ()
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// CHECK: call void @llvm.aarch64.sme.write.vert.nxv4i32
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"arm_sme.intr.write.vert"(%tile, %tileslice, %nxv4i1, %nxv4i32) :
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(i32, i32, vector<[4]xi1>, vector<[4]xi32>) -> ()
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// CHECK: call void @llvm.aarch64.sme.write.vert.nxv2i64
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"arm_sme.intr.write.vert"(%tile, %tileslice, %nxv2i1, %nxv2i64) :
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(i32, i32, vector<[2]xi1>, vector<[2]xi64>) -> ()
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// CHECK: call void @llvm.aarch64.sme.write.vert.nxv1i128
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"arm_sme.intr.write.vert"(%tile, %tileslice, %nxv1i1, %nxv1i128) :
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(i32, i32, vector<[1]xi1>, vector<[1]xi128>) -> ()
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// CHECK: call void @llvm.aarch64.sme.write.vert.nxv8f16
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"arm_sme.intr.write.vert"(%tile, %tileslice, %nxv8i1, %nxv8f16) :
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(i32, i32, vector<[8]xi1>, vector<[8]xf16>) -> ()
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// CHECK: call void @llvm.aarch64.sme.write.vert.nxv8bf16
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"arm_sme.intr.write.vert"(%tile, %tileslice, %nxv8i1, %nxv8bf16) :
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(i32, i32, vector<[8]xi1>, vector<[8]xbf16>) -> ()
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// CHECK: call void @llvm.aarch64.sme.write.vert.nxv4f32
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"arm_sme.intr.write.vert"(%tile, %tileslice, %nxv4i1, %nxv4f32) :
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(i32, i32, vector<[4]xi1>, vector<[4]xf32>) -> ()
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// CHECK: call void @llvm.aarch64.sme.write.vert.nxv2f64
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"arm_sme.intr.write.vert"(%tile, %tileslice, %nxv2i1, %nxv2f64) :
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(i32, i32, vector<[2]xi1>, vector<[2]xf64>) -> ()
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llvm.return
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}
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