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AMDGPU: Expand and modernize llvm.sqrt.f32 tests
This commit is contained in:
Matt Arsenault
parent
16bc07ac91
commit
8ce75acd1a
383
llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-sqrt.ll
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383
llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-sqrt.ll
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@ -0,0 +1,383 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
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; RUN: opt -S -mtriple=amdgcn-- -mcpu=hawaii -passes=amdgpu-codegenprepare -denormal-fp-math-f32=ieee %s | FileCheck -check-prefixes=CHECK,IEEE %s
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; RUN: opt -S -mtriple=amdgcn-- -mcpu=hawaii -passes=amdgpu-codegenprepare -denormal-fp-math-f32=dynamic %s | FileCheck -check-prefixes=CHECK,IEEE %s
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; RUN: opt -S -mtriple=amdgcn-- -mcpu=hawaii -passes=amdgpu-codegenprepare -denormal-fp-math-f32=preserve-sign %s | FileCheck -check-prefixes=CHECK,DAZ %s
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define amdgpu_kernel void @noop_sqrt_fpmath(ptr addrspace(1) %out, float %x) #0 {
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; CHECK-LABEL: define amdgpu_kernel void @noop_sqrt_fpmath
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; CHECK-SAME: (ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[MD_25ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !0
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; CHECK-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: ret void
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;
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%md.25ulp = call float @llvm.sqrt.f32(float %x), !fpmath !3
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store volatile float %md.25ulp, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @sqrt_fpmath_f32(ptr addrspace(1) %out, float %x) {
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; CHECK-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32
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; CHECK-SAME: (ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR1:[0-9]+]] {
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; CHECK-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])
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; CHECK-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1
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; CHECK-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2
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; CHECK-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_25ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !3
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; CHECK-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_3ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !0
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; CHECK-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_2ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !4
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; CHECK-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: ret void
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;
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%no.md = call float @llvm.sqrt.f32(float %x)
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store volatile float %no.md, ptr addrspace(1) %out, align 4
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%md.half.ulp = call float @llvm.sqrt.f32(float %x), !fpmath !1
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store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4
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%md.1ulp = call float @llvm.sqrt.f32(float %x), !fpmath !2
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store volatile float %md.1ulp, ptr addrspace(1) %out, align 4
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%md.25ulp = call float @llvm.sqrt.f32(float %x), !fpmath !0
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store volatile float %md.25ulp, ptr addrspace(1) %out, align 4
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%md.3ulp = call float @llvm.sqrt.f32(float %x), !fpmath !3
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store volatile float %md.3ulp, ptr addrspace(1) %out, align 4
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%md.2ulp = call float @llvm.sqrt.f32(float %x), !fpmath !4
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store volatile float %md.2ulp, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @sqrt_fpmath_v2f32(ptr addrspace(1) %out, <2 x float> %x) {
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; CHECK-LABEL: define amdgpu_kernel void @sqrt_fpmath_v2f32
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; CHECK-SAME: (ptr addrspace(1) [[OUT:%.*]], <2 x float> [[X:%.*]]) #[[ATTR1]] {
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; CHECK-NEXT: [[NO_MD:%.*]] = call <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]])
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; CHECK-NEXT: store volatile <2 x float> [[NO_MD]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_HALF_ULP:%.*]] = call <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath !1
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; CHECK-NEXT: store volatile <2 x float> [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_1ULP:%.*]] = call <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath !2
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; CHECK-NEXT: store volatile <2 x float> [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_25ULP:%.*]] = call <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath !3
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; CHECK-NEXT: store volatile <2 x float> [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_3ULP:%.*]] = call <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath !0
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; CHECK-NEXT: store volatile <2 x float> [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_2ULP:%.*]] = call <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath !4
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; CHECK-NEXT: store volatile <2 x float> [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: ret void
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;
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%no.md = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %x)
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store volatile <2 x float> %no.md, ptr addrspace(1) %out, align 4
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%md.half.ulp = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %x), !fpmath !1
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store volatile <2 x float> %md.half.ulp, ptr addrspace(1) %out, align 4
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%md.1ulp = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %x), !fpmath !2
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store volatile <2 x float> %md.1ulp, ptr addrspace(1) %out, align 4
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%md.25ulp = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %x), !fpmath !0
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store volatile <2 x float> %md.25ulp, ptr addrspace(1) %out, align 4
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%md.3ulp = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %x), !fpmath !3
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store volatile <2 x float> %md.3ulp, ptr addrspace(1) %out, align 4
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%md.2ulp = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %x), !fpmath !4
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store volatile <2 x float> %md.2ulp, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @sqrt_fpmath_f32_known_nosub(ptr addrspace(1) %out, float nofpclass(sub) %x) {
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; CHECK-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_known_nosub
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; CHECK-SAME: (ptr addrspace(1) [[OUT:%.*]], float nofpclass(sub) [[X:%.*]]) #[[ATTR1]] {
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; CHECK-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])
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; CHECK-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1
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; CHECK-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2
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; CHECK-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_25ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !3
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; CHECK-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_3ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !0
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; CHECK-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_2ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !4
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; CHECK-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: ret void
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;
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%no.md = call float @llvm.sqrt.f32(float %x)
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store volatile float %no.md, ptr addrspace(1) %out, align 4
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%md.half.ulp = call float @llvm.sqrt.f32(float %x), !fpmath !1
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store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4
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%md.1ulp = call float @llvm.sqrt.f32(float %x), !fpmath !2
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store volatile float %md.1ulp, ptr addrspace(1) %out, align 4
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%md.25ulp = call float @llvm.sqrt.f32(float %x), !fpmath !0
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store volatile float %md.25ulp, ptr addrspace(1) %out, align 4
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%md.3ulp = call float @llvm.sqrt.f32(float %x), !fpmath !3
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store volatile float %md.3ulp, ptr addrspace(1) %out, align 4
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%md.2ulp = call float @llvm.sqrt.f32(float %x), !fpmath !4
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store volatile float %md.2ulp, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero(ptr addrspace(1) %out, float nofpclass(nzero) %x) {
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; CHECK-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero
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; CHECK-SAME: (ptr addrspace(1) [[OUT:%.*]], float nofpclass(nzero) [[X:%.*]]) #[[ATTR1]] {
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; CHECK-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])
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; CHECK-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1
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; CHECK-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2
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; CHECK-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_25ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !3
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; CHECK-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_3ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !0
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; CHECK-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_2ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !4
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; CHECK-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: ret void
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;
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%no.md = call float @llvm.sqrt.f32(float %x)
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store volatile float %no.md, ptr addrspace(1) %out, align 4
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%md.half.ulp = call float @llvm.sqrt.f32(float %x), !fpmath !1
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store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4
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%md.1ulp = call float @llvm.sqrt.f32(float %x), !fpmath !2
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store volatile float %md.1ulp, ptr addrspace(1) %out, align 4
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%md.25ulp = call float @llvm.sqrt.f32(float %x), !fpmath !0
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store volatile float %md.25ulp, ptr addrspace(1) %out, align 4
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%md.3ulp = call float @llvm.sqrt.f32(float %x), !fpmath !3
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store volatile float %md.3ulp, ptr addrspace(1) %out, align 4
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%md.2ulp = call float @llvm.sqrt.f32(float %x), !fpmath !4
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store volatile float %md.2ulp, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero_nonsub(ptr addrspace(1) %out, float nofpclass(nzero nsub) %x) {
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; CHECK-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero_nonsub
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; CHECK-SAME: (ptr addrspace(1) [[OUT:%.*]], float nofpclass(nzero nsub) [[X:%.*]]) #[[ATTR1]] {
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; CHECK-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])
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; CHECK-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1
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; CHECK-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2
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; CHECK-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_25ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !3
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; CHECK-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_3ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !0
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; CHECK-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_2ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !4
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; CHECK-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: ret void
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;
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%no.md = call float @llvm.sqrt.f32(float %x)
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store volatile float %no.md, ptr addrspace(1) %out, align 4
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%md.half.ulp = call float @llvm.sqrt.f32(float %x), !fpmath !1
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store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4
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%md.1ulp = call float @llvm.sqrt.f32(float %x), !fpmath !2
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store volatile float %md.1ulp, ptr addrspace(1) %out, align 4
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%md.25ulp = call float @llvm.sqrt.f32(float %x), !fpmath !0
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store volatile float %md.25ulp, ptr addrspace(1) %out, align 4
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%md.3ulp = call float @llvm.sqrt.f32(float %x), !fpmath !3
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store volatile float %md.3ulp, ptr addrspace(1) %out, align 4
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%md.2ulp = call float @llvm.sqrt.f32(float %x), !fpmath !4
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store volatile float %md.2ulp, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero_nonsub_noinf(ptr addrspace(1) %out, float nofpclass(nzero nsub inf) %x) {
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; CHECK-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_known_nonzero_nonsub_noinf
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; CHECK-SAME: (ptr addrspace(1) [[OUT:%.*]], float nofpclass(inf nzero nsub) [[X:%.*]]) #[[ATTR1]] {
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; CHECK-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])
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; CHECK-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1
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; CHECK-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2
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; CHECK-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_25ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !3
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; CHECK-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_3ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !0
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; CHECK-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_2ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !4
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; CHECK-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: ret void
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;
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%no.md = call float @llvm.sqrt.f32(float %x)
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store volatile float %no.md, ptr addrspace(1) %out, align 4
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%md.half.ulp = call float @llvm.sqrt.f32(float %x), !fpmath !1
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store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4
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%md.1ulp = call float @llvm.sqrt.f32(float %x), !fpmath !2
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store volatile float %md.1ulp, ptr addrspace(1) %out, align 4
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%md.25ulp = call float @llvm.sqrt.f32(float %x), !fpmath !0
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store volatile float %md.25ulp, ptr addrspace(1) %out, align 4
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%md.3ulp = call float @llvm.sqrt.f32(float %x), !fpmath !3
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store volatile float %md.3ulp, ptr addrspace(1) %out, align 4
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%md.2ulp = call float @llvm.sqrt.f32(float %x), !fpmath !4
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store volatile float %md.2ulp, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @sqrt_fpmath_f32_known_nopsub(ptr addrspace(1) %out, float nofpclass(psub) %x) {
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; CHECK-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_known_nopsub
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; CHECK-SAME: (ptr addrspace(1) [[OUT:%.*]], float nofpclass(psub) [[X:%.*]]) #[[ATTR1]] {
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; CHECK-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])
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; CHECK-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1
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; CHECK-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2
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; CHECK-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_25ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !3
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; CHECK-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_3ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !0
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; CHECK-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: [[MD_2ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !4
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; CHECK-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4
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; CHECK-NEXT: ret void
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;
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%no.md = call float @llvm.sqrt.f32(float %x)
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store volatile float %no.md, ptr addrspace(1) %out, align 4
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%md.half.ulp = call float @llvm.sqrt.f32(float %x), !fpmath !1
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store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4
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%md.1ulp = call float @llvm.sqrt.f32(float %x), !fpmath !2
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store volatile float %md.1ulp, ptr addrspace(1) %out, align 4
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%md.25ulp = call float @llvm.sqrt.f32(float %x), !fpmath !0
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store volatile float %md.25ulp, ptr addrspace(1) %out, align 4
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|
||||
%md.3ulp = call float @llvm.sqrt.f32(float %x), !fpmath !3
|
||||
store volatile float %md.3ulp, ptr addrspace(1) %out, align 4
|
||||
|
||||
%md.2ulp = call float @llvm.sqrt.f32(float %x), !fpmath !4
|
||||
store volatile float %md.2ulp, ptr addrspace(1) %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sqrt_fpmath_f32_afn(ptr addrspace(1) %out, float %x) {
|
||||
; CHECK-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_afn
|
||||
; CHECK-SAME: (ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR1]] {
|
||||
; CHECK-NEXT: [[NO_MD:%.*]] = call afn float @llvm.sqrt.f32(float [[X]])
|
||||
; CHECK-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4
|
||||
; CHECK-NEXT: [[MD_HALF_ULP:%.*]] = call afn float @llvm.sqrt.f32(float [[X]]), !fpmath !1
|
||||
; CHECK-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
|
||||
; CHECK-NEXT: [[MD_1ULP:%.*]] = call afn float @llvm.sqrt.f32(float [[X]]), !fpmath !2
|
||||
; CHECK-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
|
||||
; CHECK-NEXT: [[MD_25ULP:%.*]] = call afn float @llvm.sqrt.f32(float [[X]]), !fpmath !3
|
||||
; CHECK-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
|
||||
; CHECK-NEXT: [[MD_3ULP:%.*]] = call afn float @llvm.sqrt.f32(float [[X]]), !fpmath !0
|
||||
; CHECK-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
|
||||
; CHECK-NEXT: [[MD_2ULP:%.*]] = call afn float @llvm.sqrt.f32(float [[X]]), !fpmath !4
|
||||
; CHECK-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
%no.md = call afn float @llvm.sqrt.f32(float %x)
|
||||
store volatile float %no.md, ptr addrspace(1) %out, align 4
|
||||
|
||||
%md.half.ulp = call afn float @llvm.sqrt.f32(float %x), !fpmath !1
|
||||
store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4
|
||||
|
||||
%md.1ulp = call afn float @llvm.sqrt.f32(float %x), !fpmath !2
|
||||
store volatile float %md.1ulp, ptr addrspace(1) %out, align 4
|
||||
|
||||
%md.25ulp = call afn float @llvm.sqrt.f32(float %x), !fpmath !0
|
||||
store volatile float %md.25ulp, ptr addrspace(1) %out, align 4
|
||||
|
||||
%md.3ulp = call afn float @llvm.sqrt.f32(float %x), !fpmath !3
|
||||
store volatile float %md.3ulp, ptr addrspace(1) %out, align 4
|
||||
|
||||
%md.2ulp = call afn float @llvm.sqrt.f32(float %x), !fpmath !4
|
||||
store volatile float %md.2ulp, ptr addrspace(1) %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @sqrt_fpmath_f32_assume_nosub(ptr addrspace(1) %out, float %x) {
|
||||
; CHECK-LABEL: define amdgpu_kernel void @sqrt_fpmath_f32_assume_nosub
|
||||
; CHECK-SAME: (ptr addrspace(1) [[OUT:%.*]], float [[X:%.*]]) #[[ATTR1]] {
|
||||
; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X]])
|
||||
; CHECK-NEXT: [[IS_NOT_SUBNORMAL:%.*]] = fcmp oge float [[FABS_X]], 0x3810000000000000
|
||||
; CHECK-NEXT: call void @llvm.assume(i1 [[IS_NOT_SUBNORMAL]])
|
||||
; CHECK-NEXT: [[NO_MD:%.*]] = call float @llvm.sqrt.f32(float [[X]])
|
||||
; CHECK-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4
|
||||
; CHECK-NEXT: [[MD_HALF_ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !1
|
||||
; CHECK-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
|
||||
; CHECK-NEXT: [[MD_1ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2
|
||||
; CHECK-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
|
||||
; CHECK-NEXT: [[MD_25ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !3
|
||||
; CHECK-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
|
||||
; CHECK-NEXT: [[MD_3ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !0
|
||||
; CHECK-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
|
||||
; CHECK-NEXT: [[MD_2ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !4
|
||||
; CHECK-NEXT: store volatile float [[MD_2ULP]], ptr addrspace(1) [[OUT]], align 4
|
||||
; CHECK-NEXT: [[MD_3ULP_AFN:%.*]] = call afn float @llvm.sqrt.f32(float [[X]]), !fpmath !0
|
||||
; CHECK-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
|
||||
; CHECK-NEXT: [[NO_MD_AFN:%.*]] = call afn float @llvm.sqrt.f32(float [[X]])
|
||||
; CHECK-NEXT: store volatile float [[NO_MD_AFN]], ptr addrspace(1) [[OUT]], align 4
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
%fabs.x = call float @llvm.fabs.f32(float %x)
|
||||
%is.not.subnormal = fcmp oge float %fabs.x, 0x3810000000000000
|
||||
call void @llvm.assume(i1 %is.not.subnormal)
|
||||
|
||||
%no.md = call float @llvm.sqrt.f32(float %x)
|
||||
store volatile float %no.md, ptr addrspace(1) %out, align 4
|
||||
|
||||
%md.half.ulp = call float @llvm.sqrt.f32(float %x), !fpmath !1
|
||||
store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4
|
||||
|
||||
%md.1ulp = call float @llvm.sqrt.f32(float %x), !fpmath !2
|
||||
store volatile float %md.1ulp, ptr addrspace(1) %out, align 4
|
||||
|
||||
%md.25ulp = call float @llvm.sqrt.f32(float %x), !fpmath !0
|
||||
store volatile float %md.25ulp, ptr addrspace(1) %out, align 4
|
||||
|
||||
%md.3ulp = call float @llvm.sqrt.f32(float %x), !fpmath !3
|
||||
store volatile float %md.3ulp, ptr addrspace(1) %out, align 4
|
||||
|
||||
%md.2ulp = call float @llvm.sqrt.f32(float %x), !fpmath !4
|
||||
store volatile float %md.2ulp, ptr addrspace(1) %out, align 4
|
||||
|
||||
%md.3ulp.afn = call afn float @llvm.sqrt.f32(float %x), !fpmath !3
|
||||
store volatile float %md.3ulp, ptr addrspace(1) %out, align 4
|
||||
|
||||
%no.md.afn = call afn float @llvm.sqrt.f32(float %x)
|
||||
store volatile float %no.md.afn, ptr addrspace(1) %out, align 4
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
declare float @llvm.sqrt.f32(float)
|
||||
declare <2 x float> @llvm.sqrt.v2f32(<2 x float>)
|
||||
declare float @llvm.fabs.f32(float)
|
||||
declare void @llvm.assume(i1 noundef)
|
||||
|
||||
attributes #0 = { optnone noinline }
|
||||
|
||||
!0 = !{float 2.500000e+00}
|
||||
!1 = !{float 5.000000e-01}
|
||||
!2 = !{float 1.000000e+00}
|
||||
!3 = !{float 3.000000e+00}
|
||||
!4 = !{float 2.000000e+00}
|
||||
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
||||
; DAZ: {{.*}}
|
||||
; IEEE: {{.*}}
|
||||
1316
llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
Normal file
1316
llvm/test/CodeGen/AMDGPU/fsqrt.f32.ll
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,153 +0,0 @@
|
||||
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
|
||||
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
|
||||
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
|
||||
|
||||
|
||||
; Run with unsafe-fp-math to make sure nothing tries to turn this into 1 / rsqrt(x)
|
||||
|
||||
; FUNC-LABEL: {{^}}v_safe_fsqrt_f32:
|
||||
; GCN: v_sqrt_f32_e32 {{v[0-9]+, v[0-9]+}}
|
||||
define amdgpu_kernel void @v_safe_fsqrt_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #1 {
|
||||
%r0 = load float, ptr addrspace(1) %in
|
||||
%r1 = call float @llvm.sqrt.f32(float %r0)
|
||||
store float %r1, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}v_unsafe_fsqrt_f32:
|
||||
; GCN: v_sqrt_f32_e32 {{v[0-9]+, v[0-9]+}}
|
||||
define amdgpu_kernel void @v_unsafe_fsqrt_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #2 {
|
||||
%r0 = load float, ptr addrspace(1) %in
|
||||
%r1 = call float @llvm.sqrt.f32(float %r0)
|
||||
store float %r1, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; FUNC-LABEL: {{^}}s_sqrt_f32:
|
||||
; GCN: v_sqrt_f32_e32
|
||||
|
||||
; R600: RECIPSQRT_IEEE * T{{[0-9]\.[XYZW]}}, KC0[2].Z
|
||||
; R600: RECIP_IEEE * T{{[0-9]\.[XYZW]}}, PS
|
||||
define amdgpu_kernel void @s_sqrt_f32(ptr addrspace(1) %out, float %in) #1 {
|
||||
entry:
|
||||
%fdiv = call float @llvm.sqrt.f32(float %in)
|
||||
store float %fdiv, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_sqrt_v2f32:
|
||||
; GCN: v_sqrt_f32_e32
|
||||
; GCN: v_sqrt_f32_e32
|
||||
|
||||
; R600-DAG: RECIPSQRT_IEEE * T{{[0-9]\.[XYZW]}}, KC0[2].W
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]\.[XYZW]}}, PS
|
||||
; R600-DAG: RECIPSQRT_IEEE * T{{[0-9]\.[XYZW]}}, KC0[3].X
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}
|
||||
define amdgpu_kernel void @s_sqrt_v2f32(ptr addrspace(1) %out, <2 x float> %in) #1 {
|
||||
entry:
|
||||
%fdiv = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in)
|
||||
store <2 x float> %fdiv, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}s_sqrt_v4f32:
|
||||
; GCN: v_sqrt_f32_e32
|
||||
; GCN: v_sqrt_f32_e32
|
||||
; GCN: v_sqrt_f32_e32
|
||||
; GCN: v_sqrt_f32_e32
|
||||
|
||||
; R600-DAG: RECIPSQRT_IEEE * T{{[0-9]\.[XYZW]}}, KC0[3].Y
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]\.[XYZW]}}, PS
|
||||
; R600-DAG: RECIPSQRT_IEEE * T{{[0-9]\.[XYZW]}}, KC0[3].Z
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}
|
||||
; R600-DAG: RECIPSQRT_IEEE * T{{[0-9]\.[XYZW]}}, KC0[3].W
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}
|
||||
; R600-DAG: RECIPSQRT_IEEE * T{{[0-9]\.[XYZW]}}, KC0[4].X
|
||||
; R600-DAG: RECIP_IEEE * T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}
|
||||
define amdgpu_kernel void @s_sqrt_v4f32(ptr addrspace(1) %out, <4 x float> %in) #1 {
|
||||
entry:
|
||||
%fdiv = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %in)
|
||||
store <4 x float> %fdiv, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}elim_redun_check_neg0:
|
||||
; GCN: v_sqrt_f32_e32
|
||||
; GCN-NOT: v_cndmask
|
||||
define amdgpu_kernel void @elim_redun_check_neg0(ptr addrspace(1) %out, float %in) #1 {
|
||||
entry:
|
||||
%sqrt = call float @llvm.sqrt.f32(float %in)
|
||||
%cmp = fcmp olt float %in, -0.000000e+00
|
||||
%res = select i1 %cmp, float 0x7FF8000000000000, float %sqrt
|
||||
store float %res, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}elim_redun_check_pos0:
|
||||
; GCN: v_sqrt_f32_e32
|
||||
; GCN-NOT: v_cndmask
|
||||
define amdgpu_kernel void @elim_redun_check_pos0(ptr addrspace(1) %out, float %in) #1 {
|
||||
entry:
|
||||
%sqrt = call float @llvm.sqrt.f32(float %in)
|
||||
%cmp = fcmp olt float %in, 0.000000e+00
|
||||
%res = select i1 %cmp, float 0x7FF8000000000000, float %sqrt
|
||||
store float %res, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}elim_redun_check_ult:
|
||||
; GCN: v_sqrt_f32_e32
|
||||
; GCN-NOT: v_cndmask
|
||||
define amdgpu_kernel void @elim_redun_check_ult(ptr addrspace(1) %out, float %in) #1 {
|
||||
entry:
|
||||
%sqrt = call float @llvm.sqrt.f32(float %in)
|
||||
%cmp = fcmp ult float %in, -0.000000e+00
|
||||
%res = select i1 %cmp, float 0x7FF8000000000000, float %sqrt
|
||||
store float %res, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}elim_redun_check_v2:
|
||||
; GCN: v_sqrt_f32_e32
|
||||
; GCN: v_sqrt_f32_e32
|
||||
; GCN-NOT: v_cndmask
|
||||
define amdgpu_kernel void @elim_redun_check_v2(ptr addrspace(1) %out, <2 x float> %in) #1 {
|
||||
entry:
|
||||
%sqrt = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in)
|
||||
%cmp = fcmp olt <2 x float> %in, <float -0.000000e+00, float -0.000000e+00>
|
||||
%res = select <2 x i1> %cmp, <2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>, <2 x float> %sqrt
|
||||
store <2 x float> %res, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}elim_redun_check_v2_ult
|
||||
; GCN: v_sqrt_f32_e32
|
||||
; GCN: v_sqrt_f32_e32
|
||||
; GCN-NOT: v_cndmask
|
||||
define amdgpu_kernel void @elim_redun_check_v2_ult(ptr addrspace(1) %out, <2 x float> %in) #1 {
|
||||
entry:
|
||||
%sqrt = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in)
|
||||
%cmp = fcmp ult <2 x float> %in, <float -0.000000e+00, float -0.000000e+00>
|
||||
%res = select <2 x i1> %cmp, <2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>, <2 x float> %sqrt
|
||||
store <2 x float> %res, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}recip_sqrt:
|
||||
; R600: RECIPSQRT_IEEE
|
||||
; R600-NOT: RECIP_IEEE
|
||||
define amdgpu_kernel void @recip_sqrt(ptr addrspace(1) %out, float %src) nounwind {
|
||||
%sqrt = call float @llvm.sqrt.f32(float %src)
|
||||
%recipsqrt = fdiv fast float 1.0, %sqrt
|
||||
store float %recipsqrt, ptr addrspace(1) %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
declare float @llvm.sqrt.f32(float %in) #0
|
||||
declare <2 x float> @llvm.sqrt.v2f32(<2 x float> %in) #0
|
||||
declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %in) #0
|
||||
|
||||
attributes #0 = { nounwind readnone }
|
||||
attributes #1 = { nounwind "unsafe-fp-math"="false" }
|
||||
attributes #2 = { nounwind "unsafe-fp-math"="true" }
|
||||
242
llvm/test/CodeGen/AMDGPU/fsqrt.r600.ll
Normal file
242
llvm/test/CodeGen/AMDGPU/fsqrt.r600.ll
Normal file
@ -0,0 +1,242 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
|
||||
; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
|
||||
|
||||
; Run with unsafe-fp-math to make sure nothing tries to turn this into 1 / rsqrt(x)
|
||||
|
||||
define amdgpu_kernel void @v_safe_fsqrt_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
|
||||
; R600-LABEL: v_safe_fsqrt_f32:
|
||||
; R600: ; %bb.0:
|
||||
; R600-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
|
||||
; R600-NEXT: TEX 0 @6
|
||||
; R600-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
|
||||
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
|
||||
; R600-NEXT: CF_END
|
||||
; R600-NEXT: PAD
|
||||
; R600-NEXT: Fetch clause starting at 6:
|
||||
; R600-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
|
||||
; R600-NEXT: ALU clause starting at 8:
|
||||
; R600-NEXT: MOV * T0.X, KC0[2].Z,
|
||||
; R600-NEXT: ALU clause starting at 9:
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T0.X, T0.X,
|
||||
; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
|
||||
; R600-NEXT: RECIP_IEEE * T0.X, PS,
|
||||
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
%r0 = load float, ptr addrspace(1) %in
|
||||
%r1 = call float @llvm.sqrt.f32(float %r0)
|
||||
store float %r1, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @v_unsafe_fsqrt_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #1 {
|
||||
; R600-LABEL: v_unsafe_fsqrt_f32:
|
||||
; R600: ; %bb.0:
|
||||
; R600-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
|
||||
; R600-NEXT: TEX 0 @6
|
||||
; R600-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
|
||||
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
|
||||
; R600-NEXT: CF_END
|
||||
; R600-NEXT: PAD
|
||||
; R600-NEXT: Fetch clause starting at 6:
|
||||
; R600-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
|
||||
; R600-NEXT: ALU clause starting at 8:
|
||||
; R600-NEXT: MOV * T0.X, KC0[2].Z,
|
||||
; R600-NEXT: ALU clause starting at 9:
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T0.X, T0.X,
|
||||
; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
|
||||
; R600-NEXT: RECIP_IEEE * T0.X, PS,
|
||||
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
%r0 = load float, ptr addrspace(1) %in
|
||||
%r1 = call float @llvm.sqrt.f32(float %r0)
|
||||
store float %r1, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @s_sqrt_f32(ptr addrspace(1) %out, float %in) {
|
||||
; R600-LABEL: s_sqrt_f32:
|
||||
; R600: ; %bb.0: ; %entry
|
||||
; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
|
||||
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
|
||||
; R600-NEXT: CF_END
|
||||
; R600-NEXT: PAD
|
||||
; R600-NEXT: ALU clause starting at 4:
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T0.X, KC0[2].Z,
|
||||
; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
|
||||
; R600-NEXT: RECIP_IEEE * T0.X, PS,
|
||||
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
entry:
|
||||
%fdiv = call float @llvm.sqrt.f32(float %in)
|
||||
store float %fdiv, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @s_sqrt_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
|
||||
; R600-LABEL: s_sqrt_v2f32:
|
||||
; R600: ; %bb.0: ; %entry
|
||||
; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
|
||||
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
|
||||
; R600-NEXT: CF_END
|
||||
; R600-NEXT: PAD
|
||||
; R600-NEXT: ALU clause starting at 4:
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T0.X, KC0[2].W,
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T0.Y, KC0[3].X,
|
||||
; R600-NEXT: RECIP_IEEE * T0.Y, PS,
|
||||
; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
|
||||
; R600-NEXT: RECIP_IEEE * T0.X, T0.X,
|
||||
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
entry:
|
||||
%fdiv = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in)
|
||||
store <2 x float> %fdiv, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @s_sqrt_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
|
||||
; R600-LABEL: s_sqrt_v4f32:
|
||||
; R600: ; %bb.0: ; %entry
|
||||
; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
|
||||
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
|
||||
; R600-NEXT: CF_END
|
||||
; R600-NEXT: PAD
|
||||
; R600-NEXT: ALU clause starting at 4:
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T0.X, KC0[3].Y,
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T0.Y, KC0[3].Z,
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T0.Z, KC0[3].W,
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T0.W, KC0[4].X,
|
||||
; R600-NEXT: RECIP_IEEE * T0.W, PS,
|
||||
; R600-NEXT: RECIP_IEEE * T0.Z, T0.Z,
|
||||
; R600-NEXT: RECIP_IEEE * T0.Y, T0.Y,
|
||||
; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
|
||||
; R600-NEXT: RECIP_IEEE * T0.X, T0.X,
|
||||
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
entry:
|
||||
%fdiv = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %in)
|
||||
store <4 x float> %fdiv, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @elim_redun_check_neg0(ptr addrspace(1) %out, float %in) {
|
||||
; R600-LABEL: elim_redun_check_neg0:
|
||||
; R600: ; %bb.0: ; %entry
|
||||
; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
|
||||
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
|
||||
; R600-NEXT: CF_END
|
||||
; R600-NEXT: PAD
|
||||
; R600-NEXT: ALU clause starting at 4:
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T0.X, KC0[2].Z,
|
||||
; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
|
||||
; R600-NEXT: RECIP_IEEE * T0.X, PS,
|
||||
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
entry:
|
||||
%sqrt = call float @llvm.sqrt.f32(float %in)
|
||||
%cmp = fcmp olt float %in, -0.000000e+00
|
||||
%res = select i1 %cmp, float 0x7FF8000000000000, float %sqrt
|
||||
store float %res, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @elim_redun_check_pos0(ptr addrspace(1) %out, float %in) {
|
||||
; R600-LABEL: elim_redun_check_pos0:
|
||||
; R600: ; %bb.0: ; %entry
|
||||
; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
|
||||
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
|
||||
; R600-NEXT: CF_END
|
||||
; R600-NEXT: PAD
|
||||
; R600-NEXT: ALU clause starting at 4:
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T0.X, KC0[2].Z,
|
||||
; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
|
||||
; R600-NEXT: RECIP_IEEE * T0.X, PS,
|
||||
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
entry:
|
||||
%sqrt = call float @llvm.sqrt.f32(float %in)
|
||||
%cmp = fcmp olt float %in, 0.000000e+00
|
||||
%res = select i1 %cmp, float 0x7FF8000000000000, float %sqrt
|
||||
store float %res, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @elim_redun_check_ult(ptr addrspace(1) %out, float %in) {
|
||||
; R600-LABEL: elim_redun_check_ult:
|
||||
; R600: ; %bb.0: ; %entry
|
||||
; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
|
||||
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
|
||||
; R600-NEXT: CF_END
|
||||
; R600-NEXT: PAD
|
||||
; R600-NEXT: ALU clause starting at 4:
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T0.X, KC0[2].Z,
|
||||
; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
|
||||
; R600-NEXT: RECIP_IEEE * T0.X, PS,
|
||||
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
entry:
|
||||
%sqrt = call float @llvm.sqrt.f32(float %in)
|
||||
%cmp = fcmp ult float %in, -0.000000e+00
|
||||
%res = select i1 %cmp, float 0x7FF8000000000000, float %sqrt
|
||||
store float %res, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @elim_redun_check_v2(ptr addrspace(1) %out, <2 x float> %in) {
|
||||
; R600-LABEL: elim_redun_check_v2:
|
||||
; R600: ; %bb.0: ; %entry
|
||||
; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
|
||||
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
|
||||
; R600-NEXT: CF_END
|
||||
; R600-NEXT: PAD
|
||||
; R600-NEXT: ALU clause starting at 4:
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T0.X, KC0[2].W,
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T0.Y, KC0[3].X,
|
||||
; R600-NEXT: RECIP_IEEE * T0.Y, PS,
|
||||
; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
|
||||
; R600-NEXT: RECIP_IEEE * T0.X, T0.X,
|
||||
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
entry:
|
||||
%sqrt = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in)
|
||||
%cmp = fcmp olt <2 x float> %in, <float -0.000000e+00, float -0.000000e+00>
|
||||
%res = select <2 x i1> %cmp, <2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>, <2 x float> %sqrt
|
||||
store <2 x float> %res, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @elim_redun_check_v2_ult(ptr addrspace(1) %out, <2 x float> %in) {
|
||||
; R600-LABEL: elim_redun_check_v2_ult:
|
||||
; R600: ; %bb.0: ; %entry
|
||||
; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
|
||||
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
|
||||
; R600-NEXT: CF_END
|
||||
; R600-NEXT: PAD
|
||||
; R600-NEXT: ALU clause starting at 4:
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T0.X, KC0[2].W,
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T0.Y, KC0[3].X,
|
||||
; R600-NEXT: RECIP_IEEE * T0.Y, PS,
|
||||
; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
|
||||
; R600-NEXT: RECIP_IEEE * T0.X, T0.X,
|
||||
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
entry:
|
||||
%sqrt = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in)
|
||||
%cmp = fcmp ult <2 x float> %in, <float -0.000000e+00, float -0.000000e+00>
|
||||
%res = select <2 x i1> %cmp, <2 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000>, <2 x float> %sqrt
|
||||
store <2 x float> %res, ptr addrspace(1) %out
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @recip_sqrt(ptr addrspace(1) %out, float %src) nounwind {
|
||||
; R600-LABEL: recip_sqrt:
|
||||
; R600: ; %bb.0:
|
||||
; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
|
||||
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
|
||||
; R600-NEXT: CF_END
|
||||
; R600-NEXT: PAD
|
||||
; R600-NEXT: ALU clause starting at 4:
|
||||
; R600-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
|
||||
; R600-NEXT: RECIPSQRT_IEEE * T1.X, KC0[2].Z,
|
||||
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
||||
%sqrt = call float @llvm.sqrt.f32(float %src)
|
||||
%recipsqrt = fdiv fast float 1.0, %sqrt
|
||||
store float %recipsqrt, ptr addrspace(1) %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
declare float @llvm.sqrt.f32(float %in) #0
|
||||
declare <2 x float> @llvm.sqrt.v2f32(<2 x float> %in) #0
|
||||
declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %in) #0
|
||||
|
||||
attributes #0 = { nounwind readnone }
|
||||
attributes #1 = { nounwind "unsafe-fp-math"="true" }
|
||||
Loading…
Reference in New Issue
Block a user