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Revert "[Sparc] Add Sparc V8 support"
This reverts commit r350705. llvm-svn: 350787
This commit is contained in:
Jorge Gorbe Moya
parent
03d0b0581b
commit
8d530b777d
@ -23,7 +23,6 @@
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM 287
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K 32
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS 65
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31
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#if defined(_LIBUNWIND_IS_NATIVE_ONLY)
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# if defined(__i386__)
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@ -114,11 +113,6 @@
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# error "Unsupported MIPS ABI and/or environment"
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# endif
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS
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# elif defined(__sparc__)
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#define _LIBUNWIND_TARGET_SPARC 1
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC
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#define _LIBUNWIND_CONTEXT_SIZE 16
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#define _LIBUNWIND_CURSOR_SIZE 23
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# else
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# error "Unsupported architecture."
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# endif
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@ -132,7 +126,6 @@
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# define _LIBUNWIND_TARGET_OR1K 1
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# define _LIBUNWIND_TARGET_MIPS_O32 1
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# define _LIBUNWIND_TARGET_MIPS_NEWABI 1
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# define _LIBUNWIND_TARGET_SPARC 1
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# define _LIBUNWIND_CONTEXT_SIZE 167
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# define _LIBUNWIND_CURSOR_SIZE 179
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER 287
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@ -823,40 +823,4 @@ enum {
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UNW_MIPS_LO = 65,
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};
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// SPARC registers
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enum {
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UNW_SPARC_G0 = 0,
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UNW_SPARC_G1 = 1,
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UNW_SPARC_G2 = 2,
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UNW_SPARC_G3 = 3,
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UNW_SPARC_G4 = 4,
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UNW_SPARC_G5 = 5,
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UNW_SPARC_G6 = 6,
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UNW_SPARC_G7 = 7,
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UNW_SPARC_O0 = 8,
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UNW_SPARC_O1 = 9,
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UNW_SPARC_O2 = 10,
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UNW_SPARC_O3 = 11,
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UNW_SPARC_O4 = 12,
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UNW_SPARC_O5 = 13,
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UNW_SPARC_O6 = 14,
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UNW_SPARC_O7 = 15,
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UNW_SPARC_L0 = 16,
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UNW_SPARC_L1 = 17,
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UNW_SPARC_L2 = 18,
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UNW_SPARC_L3 = 19,
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UNW_SPARC_L4 = 20,
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UNW_SPARC_L5 = 21,
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UNW_SPARC_L6 = 22,
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UNW_SPARC_L7 = 23,
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UNW_SPARC_I0 = 24,
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UNW_SPARC_I1 = 25,
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UNW_SPARC_I2 = 26,
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UNW_SPARC_I3 = 27,
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UNW_SPARC_I4 = 28,
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UNW_SPARC_I5 = 29,
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UNW_SPARC_I6 = 30,
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UNW_SPARC_I7 = 31,
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};
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#endif
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@ -223,14 +223,6 @@ int DwarfInstructions<A, R>::stepWithDwarf(A &addressSpace, pint_t pc,
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}
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#endif
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#if defined(_LIBUNWIND_TARGET_SPARC)
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// Skip call site instruction and delay slot
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returnAddress += 8;
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// Skip unimp instruction if function returns a struct
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if ((addressSpace.get32(returnAddress) & 0xC1C00000) == 0)
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returnAddress += 4;
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#endif
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// Return address is address after call site instruction, so setting IP to
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// that does simualates a return.
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newRegisters.setIP(returnAddress);
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@ -685,22 +685,6 @@ bool CFI_Parser<A>::parseInstructions(A &addressSpace, pint_t instructions,
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break;
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#endif
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#if defined(_LIBUNWIND_TARGET_SPARC)
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case DW_CFA_GNU_window_save:
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_LIBUNWIND_TRACE_DWARF("DW_CFA_GNU_window_save()\n");
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for (reg = UNW_SPARC_O0; reg <= UNW_SPARC_O7; reg++) {
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results->savedRegisters[reg].location = kRegisterInRegister;
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results->savedRegisters[reg].value =
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(reg - UNW_SPARC_O0) + UNW_SPARC_I0;
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}
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for (reg = UNW_SPARC_L0; reg <= UNW_SPARC_I7; reg++) {
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results->savedRegisters[reg].location = kRegisterInCFA;
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results->savedRegisters[reg].value = (reg - UNW_SPARC_L0) * 4;
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}
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break;
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#endif
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default:
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operand = opcode & 0x3F;
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switch (opcode & 0xC0) {
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@ -3312,194 +3312,6 @@ inline const char *Registers_mips_newabi::getRegisterName(int regNum) {
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}
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}
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#endif // _LIBUNWIND_TARGET_MIPS_NEWABI
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#if defined(_LIBUNWIND_TARGET_SPARC)
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/// Registers_sparc holds the register state of a thread in a 32-bit Sparc
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/// process.
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class _LIBUNWIND_HIDDEN Registers_sparc {
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public:
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Registers_sparc();
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Registers_sparc(const void *registers);
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bool validRegister(int num) const;
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uint32_t getRegister(int num) const;
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void setRegister(int num, uint32_t value);
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bool validFloatRegister(int num) const;
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double getFloatRegister(int num) const;
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void setFloatRegister(int num, double value);
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bool validVectorRegister(int num) const;
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v128 getVectorRegister(int num) const;
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void setVectorRegister(int num, v128 value);
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static const char *getRegisterName(int num);
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void jumpto();
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static int lastDwarfRegNum() { return _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC; }
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uint64_t getSP() const { return _registers.__regs[UNW_SPARC_O6]; }
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void setSP(uint32_t value) { _registers.__regs[UNW_SPARC_O6] = value; }
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uint64_t getIP() const { return _registers.__regs[UNW_SPARC_O7]; }
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void setIP(uint32_t value) { _registers.__regs[UNW_SPARC_O7] = value; }
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private:
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struct sparc_thread_state_t {
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unsigned int __regs[32];
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};
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sparc_thread_state_t _registers;
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};
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inline Registers_sparc::Registers_sparc(const void *registers) {
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static_assert((check_fit<Registers_sparc, unw_context_t>::does_fit),
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"sparc registers do not fit into unw_context_t");
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memcpy(&_registers, static_cast<const uint8_t *>(registers),
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sizeof(_registers));
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}
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inline Registers_sparc::Registers_sparc() {
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memset(&_registers, 0, sizeof(_registers));
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}
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inline bool Registers_sparc::validRegister(int regNum) const {
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if (regNum == UNW_REG_IP)
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return true;
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if (regNum == UNW_REG_SP)
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return true;
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if (regNum < 0)
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return false;
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if (regNum <= UNW_SPARC_I7)
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return true;
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return false;
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}
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inline uint32_t Registers_sparc::getRegister(int regNum) const {
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if ((UNW_SPARC_G0 <= regNum) && (regNum <= UNW_SPARC_I7)) {
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return _registers.__regs[regNum];
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}
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switch (regNum) {
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case UNW_REG_IP:
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return _registers.__regs[UNW_SPARC_O7];
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case UNW_REG_SP:
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return _registers.__regs[UNW_SPARC_O6];
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}
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_LIBUNWIND_ABORT("unsupported sparc register");
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}
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inline void Registers_sparc::setRegister(int regNum, uint32_t value) {
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if ((UNW_SPARC_G0 <= regNum) && (regNum <= UNW_SPARC_I7)) {
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_registers.__regs[regNum] = value;
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return;
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}
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switch (regNum) {
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case UNW_REG_IP:
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_registers.__regs[UNW_SPARC_O7] = value;
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return;
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case UNW_REG_SP:
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_registers.__regs[UNW_SPARC_O6] = value;
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return;
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}
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_LIBUNWIND_ABORT("unsupported sparc register");
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}
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inline bool Registers_sparc::validFloatRegister(int regNum) const {
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return false;
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}
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inline double Registers_sparc::getFloatRegister(int regNum) const {
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_LIBUNWIND_ABORT("no Sparc float registers");
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}
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inline void Registers_sparc::setFloatRegister(int regNum, double value) {
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_LIBUNWIND_ABORT("no Sparc float registers");
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}
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inline bool Registers_sparc::validVectorRegister(int regNum) const {
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return false;
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}
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inline v128 Registers_sparc::getVectorRegister(int regNum) const {
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_LIBUNWIND_ABORT("no Sparc vector registers");
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}
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inline void Registers_sparc::setVectorRegister(int regNum, v128 value) {
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_LIBUNWIND_ABORT("no Sparc vector registers");
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}
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inline const char *Registers_sparc::getRegisterName(int regNum) {
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switch (regNum) {
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case UNW_REG_IP:
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return "pc";
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case UNW_SPARC_G0:
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return "g0";
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case UNW_SPARC_G1:
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return "g1";
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case UNW_SPARC_G2:
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return "g2";
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case UNW_SPARC_G3:
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return "g3";
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case UNW_SPARC_G4:
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return "g4";
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case UNW_SPARC_G5:
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return "g5";
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case UNW_SPARC_G6:
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return "g6";
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case UNW_SPARC_G7:
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return "g7";
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case UNW_SPARC_O0:
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return "o0";
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case UNW_SPARC_O1:
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return "o1";
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case UNW_SPARC_O2:
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return "o2";
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case UNW_SPARC_O3:
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return "o3";
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case UNW_SPARC_O4:
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return "o4";
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case UNW_SPARC_O5:
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return "o5";
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case UNW_REG_SP:
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case UNW_SPARC_O6:
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return "sp";
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case UNW_SPARC_O7:
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return "o7";
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case UNW_SPARC_L0:
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return "l0";
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case UNW_SPARC_L1:
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return "l1";
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case UNW_SPARC_L2:
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return "l2";
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case UNW_SPARC_L3:
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return "l3";
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case UNW_SPARC_L4:
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return "l4";
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case UNW_SPARC_L5:
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return "l5";
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case UNW_SPARC_L6:
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return "l6";
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case UNW_SPARC_L7:
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return "l7";
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case UNW_SPARC_I0:
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return "i0";
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case UNW_SPARC_I1:
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return "i1";
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case UNW_SPARC_I2:
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return "i2";
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case UNW_SPARC_I3:
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return "i3";
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case UNW_SPARC_I4:
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return "i4";
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case UNW_SPARC_I5:
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return "i5";
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case UNW_SPARC_I6:
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return "fp";
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case UNW_SPARC_I7:
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return "i7";
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default:
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return "unknown register";
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}
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}
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#endif // _LIBUNWIND_TARGET_SPARC
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} // namespace libunwind
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#endif // __REGISTERS_HPP__
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@ -981,10 +981,6 @@ private:
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}
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#endif
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#if defined(_LIBUNWIND_TARGET_SPARC)
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int stepWithCompactEncoding(Registers_sparc &) { return UNW_EINVAL; }
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#endif
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bool compactSaysUseDwarf(uint32_t *offset=NULL) const {
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R dummy;
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return compactSaysUseDwarf(dummy, offset);
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@ -1046,11 +1042,6 @@ private:
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return true;
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}
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#endif
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#if defined(_LIBUNWIND_TARGET_SPARC)
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bool compactSaysUseDwarf(Registers_sparc &, uint32_t *) const { return true; }
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#endif
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#endif // defined(_LIBUNWIND_SUPPORT_COMPACT_UNWIND)
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#if defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND)
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@ -1112,11 +1103,6 @@ private:
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return 0;
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}
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#endif
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#if defined(_LIBUNWIND_TARGET_SPARC)
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compact_unwind_encoding_t dwarfEncoding(Registers_sparc &) const { return 0; }
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#endif
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#endif // defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND)
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#if defined(_LIBUNWIND_SUPPORT_SEH_UNWIND)
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@ -1000,28 +1000,6 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind21Registers_mips_newabi6jumptoEv)
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ld $4, (8 * 4)($4)
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.set pop
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#elif defined(__sparc__)
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//
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// void libunwind::Registers_sparc_o32::jumpto()
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//
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// On entry:
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// thread_state pointer is in o0
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//
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DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind15Registers_sparc6jumptoEv)
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ta 3
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ldd [%o0 + 64], %l0
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ldd [%o0 + 72], %l2
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ldd [%o0 + 80], %l4
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ldd [%o0 + 88], %l6
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ldd [%o0 + 96], %i0
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ldd [%o0 + 104], %i2
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ldd [%o0 + 112], %i4
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ldd [%o0 + 120], %i6
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ld [%o0 + 60], %o7
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jmp %o7
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nop
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#endif
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#endif /* !defined(__USING_SJLJ_EXCEPTIONS__) */
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@ -942,37 +942,9 @@ DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
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l.sw 128(r3), r9
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# zero epcr
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l.sw 132(r3), r0
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#elif defined(__sparc__)
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#
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# extern int unw_getcontext(unw_context_t* thread_state)
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#
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# On entry:
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# thread_state pointer is in o0
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#
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DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
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ta 3
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add %o7, 8, %o7
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std %g0, [%o0 + 0]
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std %g2, [%o0 + 8]
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std %g4, [%o0 + 16]
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std %g6, [%o0 + 24]
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std %o0, [%o0 + 32]
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std %o2, [%o0 + 40]
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std %o4, [%o0 + 48]
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std %o6, [%o0 + 56]
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std %l0, [%o0 + 64]
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std %l2, [%o0 + 72]
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std %l4, [%o0 + 80]
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std %l6, [%o0 + 88]
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std %i0, [%o0 + 96]
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std %i2, [%o0 + 104]
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std %i4, [%o0 + 112]
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std %i6, [%o0 + 120]
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jmp %o7
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clr %o0 // return UNW_ESUCCESS
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#endif
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#endif /* !defined(__USING_SJLJ_EXCEPTIONS__) */
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NO_EXEC_STACK_DIRECTIVE
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@ -85,8 +85,6 @@
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#define NO_EXEC_STACK_DIRECTIVE
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#elif defined(__sparc__)
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#else
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#error Unsupported target
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@ -67,8 +67,6 @@ _LIBUNWIND_EXPORT int unw_init_local(unw_cursor_t *cursor,
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# define REGISTER_KIND Registers_mips_newabi
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#elif defined(__mips__)
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# warning The MIPS architecture is not supported with this ABI and environment!
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#elif defined(__sparc__)
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# define REGISTER_KIND Registers_sparc
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#else
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# error Architecture not supported
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#endif
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