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https://github.com/capstone-engine/llvm-capstone.git
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[MC] Store operand info immediately after the TargetInsts table. NFC.
This shrinks MCInstrDesc (and hence the whole TargetInsts table) because we can store a 16-bit offset value to access the operands info, instead of a pointer. This also reduces the number of relocs that need to be applied when LLVM is compiled as position-independent code. Differential Revision: https://reviews.llvm.org/D142219
This commit is contained in:
Jay Foad
parent
1220c5d4ac
commit
8dcdc37a5f
@ -210,9 +210,9 @@ public:
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unsigned char NumImplicitUses; // Num of regs implicitly used
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unsigned char NumImplicitDefs; // Num of regs implicitly defined
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unsigned short ImplicitOffset; // Offset to start of implicit op list
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unsigned short OpInfoOffset; // Offset to info about operands
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uint64_t Flags; // Flags identifying machine instr class
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uint64_t TSFlags; // Target Specific Flag values
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const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
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/// Returns the value of the specified operand constraint if
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/// it is present. Returns -1 if it is not present.
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@ -237,7 +237,8 @@ public:
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unsigned getNumOperands() const { return NumOperands; }
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ArrayRef<MCOperandInfo> operands() const {
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return ArrayRef(OpInfo, NumOperands);
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auto OpInfo = reinterpret_cast<const MCOperandInfo *>(this + Opcode + 1);
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return ArrayRef(OpInfo + OpInfoOffset, NumOperands);
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}
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/// Return the number of MachineOperands that are register
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@ -563,8 +564,9 @@ public:
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/// reading the flags. Likewise, the variable shift instruction on X86 is
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/// marked as implicitly reading the 'CL' register, which it always does.
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ArrayRef<MCPhysReg> implicit_uses() const {
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auto ImplicitOps = reinterpret_cast<const MCPhysReg *>(this + Opcode + 1);
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return {ImplicitOps + ImplicitOffset, NumImplicitUses};
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auto ImplicitOps =
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reinterpret_cast<const MCPhysReg *>(this + Opcode + 1) + ImplicitOffset;
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return {ImplicitOps, NumImplicitUses};
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}
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/// Return a list of registers that are potentially written by any
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@ -576,8 +578,9 @@ public:
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/// registers. For that instruction, this will return a list containing the
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/// EAX/EDX/EFLAGS registers.
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ArrayRef<MCPhysReg> implicit_defs() const {
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auto ImplicitOps = reinterpret_cast<const MCPhysReg *>(this + Opcode + 1);
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return {ImplicitOps + ImplicitOffset + NumImplicitUses, NumImplicitDefs};
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auto ImplicitOps =
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reinterpret_cast<const MCPhysReg *>(this + Opcode + 1) + ImplicitOffset;
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return {ImplicitOps + NumImplicitUses, NumImplicitDefs};
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}
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/// Return true if this instruction implicitly
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@ -51,23 +51,24 @@ TEST(IsIdenticalToTest, DifferentDefs) {
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unsigned short NumOps = 2;
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unsigned char NumDefs = 1;
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MCOperandInfo OpInfo[] = {
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{0, 0, MCOI::OPERAND_REGISTER, 0},
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{0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
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MCInstrDesc MCID = {
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0, NumOps, NumDefs, 0, 0, 0, 0, 0, 1ULL << MCID::HasOptionalDef,
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0, OpInfo};
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struct {
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MCInstrDesc MCID;
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MCOperandInfo OpInfo[2];
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} Table = {
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{0, NumOps, NumDefs, 0, 0, 0, 0, 0, 0, 1ULL << MCID::HasOptionalDef, 0},
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{{0, 0, MCOI::OPERAND_REGISTER, 0},
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{0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}}};
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// Create two MIs with different virtual reg defs and the same uses.
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unsigned VirtualDef1 = -42; // The value doesn't matter, but the sign does.
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unsigned VirtualDef2 = -43;
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unsigned VirtualUse = -44;
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auto MI1 = MF->CreateMachineInstr(MCID, DebugLoc());
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auto MI1 = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
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auto MI2 = MF->CreateMachineInstr(MCID, DebugLoc());
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auto MI2 = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
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@ -83,11 +84,11 @@ TEST(IsIdenticalToTest, DifferentDefs) {
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// sentinel register.
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unsigned SentinelReg = 0;
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auto MI3 = MF->CreateMachineInstr(MCID, DebugLoc());
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auto MI3 = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
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auto MI4 = MF->CreateMachineInstr(MCID, DebugLoc());
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auto MI4 = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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MI4->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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MI4->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
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@ -122,12 +123,13 @@ TEST(MachineInstrExpressionTraitTest, IsEqualAgreesWithGetHashValue) {
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unsigned short NumOps = 2;
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unsigned char NumDefs = 1;
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MCOperandInfo OpInfo[] = {
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{0, 0, MCOI::OPERAND_REGISTER, 0},
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{0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
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MCInstrDesc MCID = {
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0, NumOps, NumDefs, 0, 0, 0, 0, 0, 1ULL << MCID::HasOptionalDef,
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0, OpInfo};
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struct {
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MCInstrDesc MCID;
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MCOperandInfo OpInfo[2];
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} Table = {
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{0, NumOps, NumDefs, 0, 0, 0, 0, 0, 0, 1ULL << MCID::HasOptionalDef, 0},
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{{0, 0, MCOI::OPERAND_REGISTER, 0},
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{0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}}};
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// Define a series of instructions with different kinds of operands and make
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// sure that the hash function is consistent with isEqual for various
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@ -138,37 +140,37 @@ TEST(MachineInstrExpressionTraitTest, IsEqualAgreesWithGetHashValue) {
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unsigned SentinelReg = 0;
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unsigned PhysicalReg = 45;
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auto VD1VU = MF->CreateMachineInstr(MCID, DebugLoc());
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auto VD1VU = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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VD1VU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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VD1VU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
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auto VD2VU = MF->CreateMachineInstr(MCID, DebugLoc());
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auto VD2VU = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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VD2VU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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VD2VU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
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auto VD1SU = MF->CreateMachineInstr(MCID, DebugLoc());
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auto VD1SU = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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VD1SU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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VD1SU->addOperand(*MF,
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MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
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auto VD1SD = MF->CreateMachineInstr(MCID, DebugLoc());
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auto VD1SD = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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VD1SD->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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VD1SD->addOperand(*MF,
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MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
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auto VD2PU = MF->CreateMachineInstr(MCID, DebugLoc());
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auto VD2PU = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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VD2PU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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VD2PU->addOperand(*MF,
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MachineOperand::CreateReg(PhysicalReg, /*isDef*/ false));
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auto VD2PD = MF->CreateMachineInstr(MCID, DebugLoc());
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auto VD2PD = MF->CreateMachineInstr(Table.MCID, DebugLoc());
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VD2PD->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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VD2PD->addOperand(*MF,
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@ -200,8 +202,11 @@ TEST(MachineInstrPrintingTest, DebugLocPrinting) {
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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MCOperandInfo OpInfo{0, 0, MCOI::OPERAND_REGISTER, 0};
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MCInstrDesc MCID = {0, 1, 1, 0, 0, 0, 0, 0, 0, 0, &OpInfo};
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struct {
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MCInstrDesc MCID;
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MCOperandInfo OpInfo;
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} Table = {{0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0},
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{0, 0, MCOI::OPERAND_REGISTER, 0}};
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DIFile *DIF = DIFile::getDistinct(Ctx, "filename", "");
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DISubprogram *DIS = DISubprogram::getDistinct(
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@ -209,7 +214,7 @@ TEST(MachineInstrPrintingTest, DebugLocPrinting) {
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DISubprogram::SPFlagZero, nullptr);
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DILocation *DIL = DILocation::get(Ctx, 1, 5, DIS);
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DebugLoc DL(DIL);
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MachineInstr *MI = MF->CreateMachineInstr(MCID, DL);
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MachineInstr *MI = MF->CreateMachineInstr(Table.MCID, DL);
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MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ true));
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std::string str;
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@ -228,7 +233,7 @@ TEST(MachineInstrSpan, DistanceBegin) {
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auto MF = createMachineFunction(Ctx, Mod);
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auto MBB = MF->CreateMachineBasicBlock();
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr};
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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auto MII = MBB->begin();
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MachineInstrSpan MIS(MII, MBB);
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@ -245,7 +250,7 @@ TEST(MachineInstrSpan, DistanceEnd) {
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auto MF = createMachineFunction(Ctx, Mod);
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auto MBB = MF->CreateMachineBasicBlock();
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr};
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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auto MII = MBB->end();
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MachineInstrSpan MIS(MII, MBB);
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@ -260,7 +265,7 @@ TEST(MachineInstrExtraInfo, AddExtraInfo) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr};
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
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auto MAI = MCAsmInfo();
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@ -320,7 +325,7 @@ TEST(MachineInstrExtraInfo, ChangeExtraInfo) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr};
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
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auto MAI = MCAsmInfo();
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@ -361,7 +366,7 @@ TEST(MachineInstrExtraInfo, RemoveExtraInfo) {
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LLVMContext Ctx;
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr};
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
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auto MAI = MCAsmInfo();
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@ -428,10 +433,9 @@ TEST(MachineInstrDebugValue, AddDebugValueOperand) {
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TargetOpcode::DBG_INSTR_REF, TargetOpcode::DBG_PHI,
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TargetOpcode::DBG_LABEL}) {
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const MCInstrDesc MCID = {
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Opcode, 0, 0,
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0, 0, 0,
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0, 0, (1ULL << MCID::Pseudo) | (1ULL << MCID::Variadic),
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0, nullptr};
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Opcode, 0, 0, 0, 0,
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0, 0, 0, 0, (1ULL << MCID::Pseudo) | (1ULL << MCID::Variadic),
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0};
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auto *MI = MF->CreateMachineInstr(MCID, DebugLoc());
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MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ false));
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@ -461,7 +465,7 @@ TEST(MachineInstrBuilder, BuildMI) {
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Module Mod("Module", Ctx);
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auto MF = createMachineFunction(Ctx, Mod);
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auto MBB = MF->CreateMachineBasicBlock();
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, nullptr};
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MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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EXPECT_THAT(BuildMI(*MF, MIMD, MCID), HasMIMetadata(MIMD));
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EXPECT_THAT(BuildMI(*MF, MIMD, MCID), HasMIMetadata(MIMD));
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EXPECT_THAT(BuildMI(*MBB, MBB->end(), MIMD, MCID), HasMIMetadata(MIMD));
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@ -64,7 +64,7 @@ enum MockInstrId {
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const std::array<MCInstrDesc, MockInstrId::TotalMockInstrs> MockInstrDescs{{
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#define MOCK_SPEC(IGNORE, OPCODE, FLAGS) \
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{OPCODE, 0, 0, 0, 0, 0, 0, 0, FLAGS, 0, nullptr},
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{OPCODE, 0, 0, 0, 0, 0, 0, 0, 0, FLAGS, 0},
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MOCK_INSTR(MOCK_SPEC)
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#undef MOCK_SPEC
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}};
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@ -61,7 +61,9 @@ public:
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private:
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void emitEnums(raw_ostream &OS);
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typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
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typedef std::vector<std::string> OperandInfoTy;
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typedef std::vector<OperandInfoTy> OperandInfoListTy;
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typedef std::map<OperandInfoTy, unsigned> OperandInfoMapTy;
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/// The keys of this map are maps which have OpName enum values as their keys
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/// and instruction operand indices as their values. The values of this map
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@ -86,9 +88,8 @@ private:
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void emitFeatureVerifier(raw_ostream &OS, const CodeGenTarget &Target);
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void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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Record *InstrInfo,
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std::map<std::vector<Record*>, unsigned> &EL,
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const OperandInfoMapTy &OpInfo,
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raw_ostream &OS);
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std::map<std::vector<Record *>, unsigned> &EL,
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const OperandInfoMapTy &OperandInfo, raw_ostream &OS);
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void emitOperandTypeMappings(
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raw_ostream &OS, const CodeGenTarget &Target,
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ArrayRef<const CodeGenInstruction *> NumberedInstructions);
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@ -108,8 +109,10 @@ private:
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ArrayRef<const CodeGenInstruction *> NumberedInstructions);
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// Operand information.
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void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
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std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
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unsigned CollectOperandInfo(OperandInfoListTy &OperandInfoList,
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OperandInfoMapTy &OperandInfoMap);
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void EmitOperandInfo(raw_ostream &OS, OperandInfoListTy &OperandInfoList);
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OperandInfoTy GetOperandInfo(const CodeGenInstruction &Inst);
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};
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} // end anonymous namespace
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@ -118,9 +121,9 @@ private:
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// Operand Info Emission.
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//===----------------------------------------------------------------------===//
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std::vector<std::string>
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InstrInfoEmitter::OperandInfoTy
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InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
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std::vector<std::string> Result;
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OperandInfoTy Result;
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for (auto &Op : Inst.Operands) {
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// Handle aggregate operands and normal operands the same way by expanding
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@ -207,23 +210,30 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
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return Result;
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}
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void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
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OperandInfoMapTy &OperandInfoIDs) {
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// ID #0 is for no operand info.
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unsigned OperandListNum = 0;
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OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
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unsigned
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InstrInfoEmitter::CollectOperandInfo(OperandInfoListTy &OperandInfoList,
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OperandInfoMapTy &OperandInfoMap) {
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const CodeGenTarget &Target = CDP.getTargetInfo();
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unsigned Offset = 0;
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for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
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std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
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unsigned &N = OperandInfoIDs[OperandInfo];
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if (N != 0) continue;
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OperandInfoTy OperandInfo = GetOperandInfo(*Inst);
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if (OperandInfoMap.insert({OperandInfo, Offset}).second) {
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OperandInfoList.push_back(OperandInfo);
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Offset += OperandInfo.size();
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}
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}
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return Offset;
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}
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N = ++OperandListNum;
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OS << "static const MCOperandInfo OperandInfo" << N << "[] = { ";
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for (const std::string &Info : OperandInfo)
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OS << "{ " << Info << " }, ";
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OS << "};\n";
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void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
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OperandInfoListTy &OperandInfoList) {
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unsigned Offset = 0;
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for (auto &OperandInfo : OperandInfoList) {
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OS << " /* " << Offset << " */";
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for (auto &Info : OperandInfo)
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OS << " { " << Info << " },";
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OS << '\n';
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Offset += OperandInfo.size();
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}
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}
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@ -886,6 +896,13 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
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const std::string &TargetName = std::string(Target.getName());
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Record *InstrInfo = Target.getInstructionSet();
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// Collect all of the operand info records.
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Records.startTimer("Collect operand info");
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OperandInfoListTy OperandInfoList;
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OperandInfoMapTy OperandInfoMap;
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unsigned OperandInfoSize =
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CollectOperandInfo(OperandInfoList, OperandInfoMap);
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// Collect all of the instruction's implicit uses and defs.
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Records.startTimer("Collect uses/defs");
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std::map<std::vector<Record*>, unsigned> EmittedLists;
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@ -908,8 +925,11 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
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OS << "struct " << TargetName << "InstrTable {\n";
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OS << " MCInstrDesc Insts[" << NumberedInstructions.size() << "];\n";
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OS << " static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "
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"\"Unwanted padding between Insts and ImplicitOps\");\n";
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OS << " static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "
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"\"Unwanted padding between Insts and OperandInfo\");\n";
|
||||
OS << " MCOperandInfo OperandInfo[" << OperandInfoSize << "];\n";
|
||||
OS << " static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "
|
||||
"\"Unwanted padding between OperandInfo and ImplicitOps\");\n";
|
||||
OS << " MCPhysReg ImplicitOps[" << std::max(ImplicitListSize, 1U) << "];\n";
|
||||
OS << "};\n\n";
|
||||
|
||||
@ -921,14 +941,12 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
|
||||
OS << "#undef GET_INSTRINFO_MC_DESC\n";
|
||||
OS << "namespace llvm {\n\n";
|
||||
|
||||
// Emit all of the operand info records.
|
||||
Records.startTimer("Emit operand info");
|
||||
OperandInfoMapTy OperandInfoIDs;
|
||||
EmitOperandInfo(OS, OperandInfoIDs);
|
||||
OS << "\n";
|
||||
|
||||
// Emit all of the MCInstrDesc records in reverse ENUM ordering.
|
||||
Records.startTimer("Emit InstrDesc records");
|
||||
OS << "static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);\n";
|
||||
OS << "static constexpr unsigned " << TargetName << "ImpOpBase = sizeof "
|
||||
<< TargetName << "InstrTable::OperandInfo / (sizeof(MCPhysReg));\n\n";
|
||||
|
||||
OS << "extern const " << TargetName << "InstrTable " << TargetName
|
||||
<< "Descs = {\n {\n";
|
||||
SequenceToOffsetTable<std::string> InstrNames;
|
||||
@ -937,11 +955,17 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
|
||||
// Keep a list of the instruction names.
|
||||
InstrNames.add(std::string(Inst->TheDef->getName()));
|
||||
// Emit the record into the table.
|
||||
emitRecord(*Inst, --Num, InstrInfo, EmittedLists, OperandInfoIDs, OS);
|
||||
emitRecord(*Inst, --Num, InstrInfo, EmittedLists, OperandInfoMap, OS);
|
||||
}
|
||||
|
||||
OS << " }, {\n";
|
||||
|
||||
// Emit all of the operand info records.
|
||||
Records.startTimer("Emit operand info");
|
||||
EmitOperandInfo(OS, OperandInfoList);
|
||||
|
||||
OS << " }, {\n";
|
||||
|
||||
// Emit all of the instruction's implicit uses and defs.
|
||||
Records.startTimer("Emit uses/defs");
|
||||
for (auto &List : ImplicitLists) {
|
||||
@ -1115,11 +1139,10 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
|
||||
emitFeatureVerifier(OS, Target);
|
||||
}
|
||||
|
||||
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
|
||||
Record *InstrInfo,
|
||||
std::map<std::vector<Record*>, unsigned> &EmittedLists,
|
||||
const OperandInfoMapTy &OpInfo,
|
||||
raw_ostream &OS) {
|
||||
void InstrInfoEmitter::emitRecord(
|
||||
const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo,
|
||||
std::map<std::vector<Record *>, unsigned> &EmittedLists,
|
||||
const OperandInfoMapTy &OperandInfoMap, raw_ostream &OS) {
|
||||
int MinOperands = 0;
|
||||
if (!Inst.Operands.empty())
|
||||
// Each logical operand can be multiple MI operands.
|
||||
@ -1131,13 +1154,18 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
|
||||
<< Inst.TheDef->getValueAsInt("Size") << ",\t"
|
||||
<< SchedModels.getSchedClassIdx(Inst) << ",\t";
|
||||
|
||||
CodeGenTarget &Target = CDP.getTargetInfo();
|
||||
|
||||
// Emit the implicit use/def list...
|
||||
OS << Inst.ImplicitUses.size() << ",\t" << Inst.ImplicitDefs.size() << ",\t";
|
||||
std::vector<Record *> ImplicitOps = Inst.ImplicitUses;
|
||||
llvm::append_range(ImplicitOps, Inst.ImplicitDefs);
|
||||
OS << EmittedLists[ImplicitOps] << ",\t0";
|
||||
OS << Target.getName() << "ImpOpBase + " << EmittedLists[ImplicitOps]
|
||||
<< ",\t";
|
||||
|
||||
CodeGenTarget &Target = CDP.getTargetInfo();
|
||||
// Emit the operand info offset.
|
||||
OperandInfoTy OperandInfo = GetOperandInfo(Inst);
|
||||
OS << OperandInfoMap.find(OperandInfo)->second << ",\t0";
|
||||
|
||||
// Emit all of the target independent flags...
|
||||
if (Inst.isPreISelOpcode) OS << "|(1ULL<<MCID::PreISelOpcode)";
|
||||
@ -1198,14 +1226,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
|
||||
}
|
||||
OS << ", 0x";
|
||||
OS.write_hex(Value);
|
||||
OS << "ULL, ";
|
||||
|
||||
// Emit the operand info.
|
||||
std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
|
||||
if (OperandInfo.empty())
|
||||
OS << "nullptr";
|
||||
else
|
||||
OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
|
||||
OS << "ULL";
|
||||
|
||||
OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user