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[SiFive][RISCV][clang] Support C intrinsics for xsfvcp extension.
Depends on D147934 and D147935 Differential Revision: https://reviews.llvm.org/D148223
This commit is contained in:
Nelson Chu
4vtomat
parent
4b2381a5f0
commit
8ed9cf06e9
103
clang/include/clang/Basic/riscv_sifive_vector.td
Normal file
103
clang/include/clang/Basic/riscv_sifive_vector.td
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@ -0,0 +1,103 @@
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//==--- riscv_sifive_vector.td - RISC-V SiFive VCIX function list ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the builtins for RISC-V SiFive VCIX. See:
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//
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// https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction definitions
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//===----------------------------------------------------------------------===//
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class VCIXSuffix<string range> {
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list<string> suffix = !cond(!eq(range, "c"): ["8mf8", "8mf4", "8mf2", "8m1", "8m2", "8m4", "8m8"],
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!eq(range, "s"): ["16mf4", "16mf2", "16m1", "16m2", "16m4", "16m8"],
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!eq(range, "i"): ["32mf2", "32m1", "32m2", "32m4", "32m8"],
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!eq(range, "l"): ["64m1", "64m2", "64m4", "64m8"]);
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}
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class VCIXBuiltinSet<string name, string IR_name, string suffix,
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string prototype, string type_range,
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list<int> intrinsic_types>
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: RVVBuiltin<suffix, prototype, type_range> {
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let Name = name;
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let OverloadedName = name;
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let IRName = IR_name;
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let HasMasked = false;
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let IntrinsicTypes = intrinsic_types;
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}
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multiclass VCIXBuiltinSet<string name, string IR_name, string suffix,
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string prototype, string type_range,
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list<int> intrinsic_types> {
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if !find(prototype, "0") then {
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def : VCIXBuiltinSet<name, IR_name, suffix, prototype, type_range, intrinsic_types>;
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}
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def : VCIXBuiltinSet<name # "_se", IR_name # "_se", suffix, prototype, type_range, intrinsic_types>;
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}
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multiclass RVVVCIXBuiltinSet<list<string> range, string prototype,
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list<int> intrinsic_types, bit UseGPR> {
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foreach r = range in
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let RequiredFeatures = !if(!and(UseGPR, !eq(r, "l")),
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["Xsfvcp", "RV64"], ["Xsfvcp"]) in
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defm : VCIXBuiltinSet<NAME, NAME, "Uv", prototype, r, intrinsic_types>;
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}
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multiclass RVVVCIXBuiltinSetWVType<list<string> range, string prototype,
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list<int> intrinsic_types, bit UseGPR> {
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foreach r = range in
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let RequiredFeatures = !if(!and(UseGPR, !eq(r, "l")),
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["Xsfvcp", "RV64"], ["Xsfvcp"]) in
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// These intrinsics don't have any vector types in the output and inputs,
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// but we still need to add vetvli for them. So we encode different
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// VTYPE into the intrinsic names, and then will know which vsetvli is
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// correct.
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foreach s = VCIXSuffix<r>.suffix in
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// Since we already encode the Vtype into the name, so just set
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// Log2LMUL to zero. Otherwise the RISCVVEmitter will expand
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// lots of redundant intrinsic but have same names.
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let Log2LMUL = [0] in
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def : VCIXBuiltinSet<NAME # "_u" # s, NAME # "_e" # s,
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"", prototype, r, intrinsic_types>;
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}
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let SupportOverloading = false in {
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defm sf_vc_x_se : RVVVCIXBuiltinSetWVType<["c", "s", "i", "l"], "0KzKzKzUe", [0, 3], /*UseGPR*/1>;
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defm sf_vc_i_se : RVVVCIXBuiltinSetWVType<["c", "s", "i", "l"], "0KzKzKzKz", [2, 3], /*UseGPR*/0>;
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defm sf_vc_xv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUe", [0, 2, 3], /*UseGPR*/1>;
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defm sf_vc_iv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvKz", [0, 2, 3], /*UseGPR*/0>;
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defm sf_vc_vv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUv", [0, 2, 3], /*UseGPR*/0>;
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defm sf_vc_fv : RVVVCIXBuiltinSet<["si", "l"], "0KzKzUvFe", [0, 2, 3], /*UseGPR*/0>;
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defm sf_vc_xvv : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvUe", [0, 1, 3], /*UseGPR*/1>;
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defm sf_vc_ivv : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvKz", [0, 1, 3], /*UseGPR*/0>;
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defm sf_vc_vvv : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvUv", [0, 1, 3], /*UseGPR*/0>;
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defm sf_vc_fvv : RVVVCIXBuiltinSet<["si", "l"], "0KzUvUvFe", [0, 1, 3], /*UseGPR*/0>;
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defm sf_vc_v_x : RVVVCIXBuiltinSet<["csi", "l"], "UvKzKzUe", [-1, 1, 2], /*UseGPR*/1>;
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defm sf_vc_v_i : RVVVCIXBuiltinSet<["csi", "l"], "UvKzKzKz", [-1, 1, 2], /*UseGPR*/0>;
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defm sf_vc_v_xv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUe", [-1, 0, 2], /*UseGPR*/1>;
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defm sf_vc_v_iv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvKz", [-1, 0, 2], /*UseGPR*/0>;
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defm sf_vc_v_vv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUv", [-1, 0, 2], /*UseGPR*/0>;
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defm sf_vc_v_fv : RVVVCIXBuiltinSet<["si", "l"], "UvKzUvFe", [-1, 0, 2], /*UseGPR*/0>;
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defm sf_vc_v_xvv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUvUe", [-1, 0, 3], /*UseGPR*/1>;
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defm sf_vc_v_ivv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUvKz", [-1, 0, 3], /*UseGPR*/0>;
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defm sf_vc_v_vvv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUvUv", [-1, 0, 3], /*UseGPR*/0>;
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defm sf_vc_v_fvv : RVVVCIXBuiltinSet<["si", "l"], "UvKzUvUvFe", [-1, 0, 3], /*UseGPR*/0>;
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let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
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defm sf_vc_xvw : RVVVCIXBuiltinSet<["csi"], "0KzUwUvUe", [0, 1, 2, 3], /*UseGPR*/1>;
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defm sf_vc_ivw : RVVVCIXBuiltinSet<["csi"], "0KzUwUvKz", [0, 1, 2, 3], /*UseGPR*/0>;
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defm sf_vc_vvw : RVVVCIXBuiltinSet<["csi"], "0KzUwUvUv", [0, 1, 2, 3], /*UseGPR*/0>;
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defm sf_vc_fvw : RVVVCIXBuiltinSet<["si"], "0KzUwUvFe", [0, 1, 2, 3], /*UseGPR*/0>;
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defm sf_vc_v_xvw : RVVVCIXBuiltinSet<["csi"], "UwKzUwUvUe", [-1, 0, 2, 3], /*UseGPR*/1>;
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defm sf_vc_v_ivw : RVVVCIXBuiltinSet<["csi"], "UwKzUwUvKz", [-1, 0, 2, 3], /*UseGPR*/0>;
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defm sf_vc_v_vvw : RVVVCIXBuiltinSet<["csi"], "UwKzUwUvUv", [-1, 0, 2, 3], /*UseGPR*/0>;
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defm sf_vc_v_fvw : RVVVCIXBuiltinSet<["si"], "UwKzUwUvFe", [-1, 0, 2, 3], /*UseGPR*/0>;
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}
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}
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@ -2374,3 +2374,5 @@ let HasMasked = false, HasVL = false, IRName = "" in {
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}
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}
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}
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include "riscv_sifive_vector.td"
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@ -4641,6 +4641,127 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
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(VecInfo.EC.getKnownMinValue() * VecInfo.NumVectors);
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return SemaBuiltinConstantArgRange(TheCall, 1, 0, MaxIndex - 1);
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}
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8mf8:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8mf4:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8mf2:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8m1:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8m2:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8m4:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8m8:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16mf4:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16mf2:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16m1:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16m2:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16m4:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u16m8:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32mf2:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32m1:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32m2:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32m4:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u32m8:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u64m1:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u64m2:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u64m4:
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case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u64m8:
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// bit_27_26, bit_24_20, bit_11_7, simm5
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return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
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SemaBuiltinConstantArgRange(TheCall, 1, 0, 31) ||
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SemaBuiltinConstantArgRange(TheCall, 2, 0, 31) ||
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SemaBuiltinConstantArgRange(TheCall, 3, -16, 15);
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case RISCVVector::BI__builtin_rvv_sf_vc_iv_se:
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// bit_27_26, bit_11_7, vs2, simm5
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return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
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SemaBuiltinConstantArgRange(TheCall, 1, 0, 31) ||
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SemaBuiltinConstantArgRange(TheCall, 3, -16, 15);
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case RISCVVector::BI__builtin_rvv_sf_vc_v_i:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_i_se:
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// bit_27_26, bit_24_20, simm5
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return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
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SemaBuiltinConstantArgRange(TheCall, 1, 0, 31) ||
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SemaBuiltinConstantArgRange(TheCall, 2, -16, 15);
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case RISCVVector::BI__builtin_rvv_sf_vc_v_iv:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_iv_se:
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// bit_27_26, vs2, simm5
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return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
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SemaBuiltinConstantArgRange(TheCall, 2, -16, 15);
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case RISCVVector::BI__builtin_rvv_sf_vc_ivv_se:
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case RISCVVector::BI__builtin_rvv_sf_vc_ivw_se:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_ivv:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_ivw:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_ivv_se:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_ivw_se:
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// bit_27_26, vd, vs2, simm5
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return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
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SemaBuiltinConstantArgRange(TheCall, 3, -16, 15);
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8mf8:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8mf4:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8mf2:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8m1:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8m2:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8m4:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u8m8:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16mf4:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16mf2:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16m1:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16m2:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16m4:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u16m8:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32mf2:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32m1:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32m2:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32m4:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u32m8:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u64m1:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u64m2:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u64m4:
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case RISCVVector::BI__builtin_rvv_sf_vc_x_se_u64m8:
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// bit_27_26, bit_24_20, bit_11_7, xs1
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return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
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SemaBuiltinConstantArgRange(TheCall, 1, 0, 31) ||
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SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
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case RISCVVector::BI__builtin_rvv_sf_vc_xv_se:
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case RISCVVector::BI__builtin_rvv_sf_vc_vv_se:
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// bit_27_26, bit_11_7, vs2, xs1/vs1
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case RISCVVector::BI__builtin_rvv_sf_vc_v_x:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_x_se:
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// bit_27_26, bit_24-20, xs1
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return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
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SemaBuiltinConstantArgRange(TheCall, 1, 0, 31);
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case RISCVVector::BI__builtin_rvv_sf_vc_vvv_se:
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case RISCVVector::BI__builtin_rvv_sf_vc_xvv_se:
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case RISCVVector::BI__builtin_rvv_sf_vc_vvw_se:
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case RISCVVector::BI__builtin_rvv_sf_vc_xvw_se:
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// bit_27_26, vd, vs2, xs1
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case RISCVVector::BI__builtin_rvv_sf_vc_v_xv:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_vv:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_xv_se:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_vv_se:
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// bit_27_26, vs2, xs1/vs1
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case RISCVVector::BI__builtin_rvv_sf_vc_v_xvv:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_vvv:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_xvw:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_vvw:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_xvv_se:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_vvv_se:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_xvw_se:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_vvw_se:
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// bit_27_26, vd, vs2, xs1/vs1
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return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3);
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case RISCVVector::BI__builtin_rvv_sf_vc_fv_se:
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// bit_26, bit_11_7, vs2, fs1
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return SemaBuiltinConstantArgRange(TheCall, 0, 0, 1) ||
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SemaBuiltinConstantArgRange(TheCall, 1, 0, 31);
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case RISCVVector::BI__builtin_rvv_sf_vc_fvv_se:
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case RISCVVector::BI__builtin_rvv_sf_vc_fvw_se:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_fvv:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_fvw:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_fvv_se:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_fvw_se:
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// bit_26, vd, vs2, fs1
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case RISCVVector::BI__builtin_rvv_sf_vc_v_fv:
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case RISCVVector::BI__builtin_rvv_sf_vc_v_fv_se:
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// bit_26, vs2, fs1
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return SemaBuiltinConstantArgRange(TheCall, 0, 0, 1);
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// Check if byteselect is in [0, 3]
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case RISCV::BI__builtin_riscv_aes32dsi_32:
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case RISCV::BI__builtin_riscv_aes32dsmi_32:
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@ -0,0 +1,116 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
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#include <riscv_vector.h>
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#define p27_26 (0b11)
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#define p24_20 (0b11111)
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#define p11_7 (0b11111)
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// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e64m1.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret void
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//
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void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {
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__riscv_sf_vc_x_se_u64m1(p27_26, p24_20, p11_7, rs1, vl);
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}
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// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m2(
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// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e64m2.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret void
|
||||
//
|
||||
void test_sf_vc_x_se_u64m2(uint64_t rs1, size_t vl) {
|
||||
__riscv_sf_vc_x_se_u64m2(p27_26, p24_20, p11_7, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m4(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e64m4.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret void
|
||||
//
|
||||
void test_sf_vc_x_se_u64m4(uint64_t rs1, size_t vl) {
|
||||
__riscv_sf_vc_x_se_u64m4(p27_26, p24_20, p11_7, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m8(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e64m8.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret void
|
||||
//
|
||||
void test_sf_vc_x_se_u64m8(uint64_t rs1, size_t vl) {
|
||||
__riscv_sf_vc_x_se_u64m8(p27_26, p24_20, p11_7, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u64m1(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m1_t test_sf_vc_v_x_se_u64m1(uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_x_se_u64m1(p27_26, p24_20, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u64m2(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m2_t test_sf_vc_v_x_se_u64m2(uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_x_se_u64m2(p27_26, p24_20, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u64m4(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m4_t test_sf_vc_v_x_se_u64m4(uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_x_se_u64m4(p27_26, p24_20, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u64m8(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m8_t test_sf_vc_v_x_se_u64m8(uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_x_se_u64m8(p27_26, p24_20, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_x_u64m1(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m1_t test_sf_vc_v_x_u64m1(uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_x_u64m1(p27_26, p24_20, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_x_u64m2(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m2_t test_sf_vc_v_x_u64m2(uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_x_u64m2(p27_26, p24_20, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_x_u64m4(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m4_t test_sf_vc_v_x_u64m4(uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_x_u64m4(p27_26, p24_20, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_x_u64m8(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m8_t test_sf_vc_v_x_u64m8(uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_x_u64m8(p27_26, p24_20, rs1, vl);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,116 @@
|
||||
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
|
||||
// REQUIRES: riscv-registered-target
|
||||
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
|
||||
|
||||
#include <riscv_vector.h>
|
||||
|
||||
#define p27_26 (0b11)
|
||||
#define p11_7 (0b11111)
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u64m1(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 3, i64 31, <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret void
|
||||
//
|
||||
void test_sf_vc_xv_se_u64m1(vuint64m1_t vs2, uint64_t rs1, size_t vl) {
|
||||
__riscv_sf_vc_xv_se_u64m1(p27_26, p11_7, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u64m2(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 3, i64 31, <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret void
|
||||
//
|
||||
void test_sf_vc_xv_se_u64m2(vuint64m2_t vs2, uint64_t rs1, size_t vl) {
|
||||
__riscv_sf_vc_xv_se_u64m2(p27_26, p11_7, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u64m4(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 3, i64 31, <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret void
|
||||
//
|
||||
void test_sf_vc_xv_se_u64m4(vuint64m4_t vs2, uint64_t rs1, size_t vl) {
|
||||
__riscv_sf_vc_xv_se_u64m4(p27_26, p11_7, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u64m8(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 3, i64 31, <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret void
|
||||
//
|
||||
void test_sf_vc_xv_se_u64m8(vuint64m8_t vs2, uint64_t rs1, size_t vl) {
|
||||
__riscv_sf_vc_xv_se_u64m8(p27_26, p11_7, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u64m1(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.i64.i64(i64 3, <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m1_t test_sf_vc_v_xv_se_u64m1(vuint64m1_t vs2, uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_xv_se_u64m1(p27_26, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u64m2(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.i64.i64(i64 3, <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m2_t test_sf_vc_v_xv_se_u64m2(vuint64m2_t vs2, uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_xv_se_u64m2(p27_26, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u64m4(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.i64.i64(i64 3, <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m4_t test_sf_vc_v_xv_se_u64m4(vuint64m4_t vs2, uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_xv_se_u64m4(p27_26, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u64m8(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.i64.i64(i64 3, <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m8_t test_sf_vc_v_xv_se_u64m8(vuint64m8_t vs2, uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_xv_se_u64m8(p27_26, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u64m1(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.i64.i64(i64 3, <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m1_t test_sf_vc_v_xv_u64m1(vuint64m1_t vs2, uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_xv_u64m1(p27_26, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u64m2(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.i64.i64(i64 3, <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m2_t test_sf_vc_v_xv_u64m2(vuint64m2_t vs2, uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_xv_u64m2(p27_26, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u64m4(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.i64.i64(i64 3, <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m4_t test_sf_vc_v_xv_u64m4(vuint64m4_t vs2, uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_xv_u64m4(p27_26, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u64m8(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xv.nxv8i64.i64.i64.i64(i64 3, <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m8_t test_sf_vc_v_xv_u64m8(vuint64m8_t vs2, uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_xv_u64m8(p27_26, vs2, rs1, vl);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,115 @@
|
||||
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
|
||||
// REQUIRES: riscv-registered-target
|
||||
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
|
||||
|
||||
#include <riscv_vector.h>
|
||||
|
||||
#define p27_26 (0b11)
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u64m1(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret void
|
||||
//
|
||||
void test_sf_vc_xvv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, uint64_t rs1, size_t vl) {
|
||||
__riscv_sf_vc_xvv_se_u64m1(p27_26, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u64m2(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.i64.i64(i64 3, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret void
|
||||
//
|
||||
void test_sf_vc_xvv_se_u64m2(vuint64m2_t vd, vuint64m2_t vs2, uint64_t rs1, size_t vl) {
|
||||
__riscv_sf_vc_xvv_se_u64m2(p27_26, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u64m4(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.i64.i64(i64 3, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret void
|
||||
//
|
||||
void test_sf_vc_xvv_se_u64m4(vuint64m4_t vd, vuint64m4_t vs2, uint64_t rs1, size_t vl) {
|
||||
__riscv_sf_vc_xvv_se_u64m4(p27_26, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u64m8(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.i64.i64(i64 3, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret void
|
||||
//
|
||||
void test_sf_vc_xvv_se_u64m8(vuint64m8_t vd, vuint64m8_t vs2, uint64_t rs1, size_t vl) {
|
||||
__riscv_sf_vc_xvv_se_u64m8(p27_26, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u64m1(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.i64.i64(i64 3, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m1_t test_sf_vc_v_xvv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_xvv_se_u64m1(p27_26, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u64m2(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.i64.i64(i64 3, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m2_t test_sf_vc_v_xvv_se_u64m2(vuint64m2_t vd, vuint64m2_t vs2, uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_xvv_se_u64m2(p27_26, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u64m4(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.i64.i64(i64 3, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m4_t test_sf_vc_v_xvv_se_u64m4(vuint64m4_t vd, vuint64m4_t vs2, uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_xvv_se_u64m4(p27_26, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u64m8(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.i64.i64(i64 3, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m8_t test_sf_vc_v_xvv_se_u64m8(vuint64m8_t vd, vuint64m8_t vs2, uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_xvv_se_u64m8(p27_26, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u64m1(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.i64.i64(i64 3, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m1_t test_sf_vc_v_xvv_u64m1(vuint64m1_t vd, vuint64m1_t vs2, uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_xvv_u64m1(p27_26, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u64m2(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xvv.nxv2i64.i64.i64.i64(i64 3, <vscale x 2 x i64> [[VD:%.*]], <vscale x 2 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m2_t test_sf_vc_v_xvv_u64m2(vuint64m2_t vd, vuint64m2_t vs2, uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_xvv_u64m2(p27_26, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u64m4(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xvv.nxv4i64.i64.i64.i64(i64 3, <vscale x 4 x i64> [[VD:%.*]], <vscale x 4 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m4_t test_sf_vc_v_xvv_u64m4(vuint64m4_t vd, vuint64m4_t vs2, uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_xvv_u64m4(p27_26, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u64m8(
|
||||
// CHECK-RV64-NEXT: entry:
|
||||
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xvv.nxv8i64.i64.i64.i64(i64 3, <vscale x 8 x i64> [[VD:%.*]], <vscale x 8 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
|
||||
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
||||
//
|
||||
vuint64m8_t test_sf_vc_v_xvv_u64m8(vuint64m8_t vd, vuint64m8_t vs2, uint64_t rs1, size_t vl) {
|
||||
return __riscv_sf_vc_v_xvv_u64m8(p27_26, vd, vs2, rs1, vl);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,764 @@
|
||||
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
|
||||
// REQUIRES: riscv-registered-target
|
||||
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
|
||||
// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
|
||||
// RUN: -target-feature +xsfvcp \
|
||||
// RUN: -fsyntax-only -verify %s
|
||||
|
||||
#include <riscv_vector.h>
|
||||
|
||||
#define p27_26 (0b11)
|
||||
#define p26 (0b1)
|
||||
#define p24_20 (0b11111)
|
||||
#define p11_7 (0b11111)
|
||||
#define simm5 (15)
|
||||
|
||||
#define p27_26_overflow (0b100)
|
||||
#define p26_overflow (0b10)
|
||||
#define p24_20_overflow (0b100000)
|
||||
#define p11_7_overflow (0b100001)
|
||||
#define simm5_overflow (16)
|
||||
|
||||
// sf_vc_x_se
|
||||
|
||||
void test_sf_vc_x_se_u8mf8_p27_26_not_constant(uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_x_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_x_se_u8mf8(index, p24_20, p11_7, rs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_x_se_u8mf8_24_20_not_constant(uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_x_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_x_se_u8mf8(p27_26, index, p11_7, rs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_x_se_u8mf8_11_7_not_constant(uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_x_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_x_se_u8mf8(p27_26, p24_20, index, rs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_x_se_u8mf8_p27_26_overflow(uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
__riscv_sf_vc_x_se_u8mf8(p27_26_overflow, p24_20, p11_7, rs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_x_se_u8mf8_p24_20_overflow(uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 32 is outside the valid range [0, 31]}}
|
||||
__riscv_sf_vc_x_se_u8mf8(p27_26, p24_20_overflow, p11_7, rs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_x_se_u8mf8_p11_7_overflow(uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 33 is outside the valid range [0, 31]}}
|
||||
__riscv_sf_vc_x_se_u8mf8(p27_26, p24_20, p11_7_overflow, rs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_i_se
|
||||
|
||||
void test_sf_vc_i_se_u8mf8_p27_26_not_constant(size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_i_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_i_se_u8mf8(index, p24_20, p11_7, simm5, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_i_se_u8mf8_24_20_not_constant(size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_i_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_i_se_u8mf8(p27_26, index, p11_7, simm5, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_i_se_u8mf8_11_7_not_constant(size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_i_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_i_se_u8mf8(p27_26, p24_20, index, simm5, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_i_se_u8mf8_simm5_not_constant(size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_i_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_i_se_u8mf8(p27_26, p24_20, p11_7, index, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_i_se_u8mf8_p27_26_overflow(size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
__riscv_sf_vc_i_se_u8mf8(p27_26_overflow, p24_20, p11_7, simm5, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_i_se_u8mf8_p24_20_overflow(size_t vl) {
|
||||
// expected-error@+1 {{argument value 32 is outside the valid range [0, 31]}}
|
||||
__riscv_sf_vc_i_se_u8mf8(p27_26, p24_20_overflow, p11_7, simm5, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_i_se_u8mf8_p11_7_overflow(size_t vl) {
|
||||
// expected-error@+1 {{argument value 33 is outside the valid range [0, 31]}}
|
||||
__riscv_sf_vc_i_se_u8mf8(p27_26, p24_20, p11_7_overflow, simm5, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_i_se_u8mf8_simm5_overflow(size_t vl) {
|
||||
// expected-error@+1 {{argument value 16 is outside the valid range [-16, 15]}}
|
||||
__riscv_sf_vc_i_se_u8mf8(p27_26, p24_20, p11_7, simm5_overflow, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_x_se
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_x_se_u8mf8_p27_26_not_constant(uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_x_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_x_se_u8mf8(index, p24_20, rs1, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_x_se_u8mf8_p24_20_not_constant(uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_x_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_x_se_u8mf8(p27_26, index, rs1, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_x_se_u8mf8_p27_26_overflow(uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_x_se_u8mf8(p27_26_overflow, p24_20, rs1, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_x_se_u8mf8_p24_20_overflow(uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 32 is outside the valid range [0, 31]}}
|
||||
return __riscv_sf_vc_v_x_se_u8mf8(p27_26, p24_20_overflow, rs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_x
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_x_u8mf8_p27_26_not_constant(uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_x_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_x_u8mf8(index, p24_20, rs1, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_x_u8mf8_p24_20_not_constant(uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_x_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_x_u8mf8(p27_26, index, rs1, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_x_u8mf8_p27_26_overflow(uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_x_u8mf8(p27_26_overflow, p24_20, rs1, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_x_u8mf8_p24_20_overflow(uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 32 is outside the valid range [0, 31]}}
|
||||
return __riscv_sf_vc_v_x_u8mf8(p27_26, p24_20_overflow, rs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_i_se
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_i_se_u8mf8_p27_26_not_constant(size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_i_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_i_se_u8mf8(index, p24_20, simm5, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_i_se_u8mf8_p24_20_not_constant(size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_i_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_i_se_u8mf8(p27_26, index, simm5, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_i_se_u8mf8_simm5_not_constant(size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_i_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_i_se_u8mf8(p27_26, p24_20, index, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_i_se_u8mf8_p27_26_overflow(size_t vl, int index) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_i_se_u8mf8(p27_26_overflow, p24_20, simm5, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_i_se_u8mf8_p24_20_overflow(size_t vl) {
|
||||
// expected-error@+1 {{argument value 32 is outside the valid range [0, 31]}}
|
||||
return __riscv_sf_vc_v_i_se_u8mf8(p27_26, p24_20_overflow, simm5, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_i_se_u8mf8_simm5_overflow(size_t vl) {
|
||||
// expected-error@+1 {{argument value 16 is outside the valid range [-16, 15]}}
|
||||
return __riscv_sf_vc_v_i_se_u8mf8(p27_26, p24_20, simm5_overflow, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_i
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_i_u8mf8_p27_26_not_constant(size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_i_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_i_u8mf8(index, p24_20, simm5, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_i_u8mf8_p24_20_not_constant(size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_i_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_i_u8mf8(p27_26, index, simm5, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_i_u8mf8_simm5_not_constant(size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_i_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_i_u8mf8(p27_26, p24_20, index, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_i_u8mf8_p27_26_overflow(size_t vl, int index) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_i_u8mf8(p27_26_overflow, p24_20, simm5, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_i_u8mf8_p24_20_overflow(size_t vl) {
|
||||
// expected-error@+1 {{argument value 32 is outside the valid range [0, 31]}}
|
||||
return __riscv_sf_vc_v_i_u8mf8(p27_26, p24_20_overflow, simm5, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_i_u8mf8_simm5_overflow(size_t vl) {
|
||||
// expected-error@+1 {{argument value 16 is outside the valid range [-16, 15]}}
|
||||
return __riscv_sf_vc_v_i_u8mf8(p27_26, p24_20, simm5_overflow, vl);
|
||||
}
|
||||
|
||||
// sf_vc_vv_se
|
||||
|
||||
void test_sf_vc_vv_se_u8mf8_p27_26_not_constant(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_vv_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_vv_se_u8mf8(index, p11_7, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_vv_se_u8mf8_p11_7_not_constant(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_vv_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_vv_se_u8mf8(p27_26, index, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_vv_se_u8mf8_p27_26_overflow(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
__riscv_sf_vc_vv_se_u8mf8(p27_26_overflow, p11_7, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_vv_se_u8mf8_p11_7_overflow(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 33 is outside the valid range [0, 31]}}
|
||||
__riscv_sf_vc_vv_se_u8mf8(p27_26, p11_7_overflow, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_xv_se
|
||||
|
||||
void test_sf_vc_xv_se_u8mf8_p27_26_not_constant(vuint8mf8_t vs2, uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_xv_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_xv_se_u8mf8(index, p11_7, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_xv_se_u8mf8_p11_7_not_constant(vuint8mf8_t vs2, uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_xv_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_xv_se_u8mf8(p27_26, index, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_xv_se_u8mf8_p27_26_overflow(vuint8mf8_t vs2, uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
__riscv_sf_vc_xv_se_u8mf8(p27_26_overflow, p11_7, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_xv_se_u8mf8_p11_7_overflow(vuint8mf8_t vs2, uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 33 is outside the valid range [0, 31]}}
|
||||
__riscv_sf_vc_xv_se_u8mf8(p27_26, p11_7_overflow, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_iv_se
|
||||
|
||||
void test_sf_vc_iv_se_u8mf8_p27_26_not_constant(vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_iv_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_iv_se_u8mf8(index, p11_7, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_iv_se_u8mf8_p11_7_not_constant(vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_iv_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_iv_se_u8mf8(p27_26, index, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_iv_se_u8mf8_simm5_not_constant(vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_iv_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_iv_se_u8mf8(p27_26, p11_7, vs2, index, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_iv_se_u8mf8_p27_26_overflow(vuint8mf8_t vs2, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
__riscv_sf_vc_iv_se_u8mf8(p27_26_overflow, p11_7, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_iv_se_u8mf8_p11_7_overflow(vuint8mf8_t vs2, size_t vl) {
|
||||
// expected-error@+1 {{argument value 33 is outside the valid range [0, 31]}}
|
||||
__riscv_sf_vc_iv_se_u8mf8(p27_26, p11_7_overflow, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_iv_se_u8mf8_simm5_overflow(vuint8mf8_t vs2, size_t vl) {
|
||||
// expected-error@+1 {{argument value 16 is outside the valid range [-16, 15]}}
|
||||
__riscv_sf_vc_iv_se_u8mf8(p27_26, p11_7, vs2, simm5_overflow, vl);
|
||||
}
|
||||
|
||||
// sf_vc_fv_se
|
||||
|
||||
void test_sf_vc_fv_se_u16mf4_p26_not_constant(vuint16mf4_t vs2, _Float16 fs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_fv_se_u16mf4' must be a constant integer}}
|
||||
__riscv_sf_vc_fv_se_u16mf4(index, p11_7, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_fv_se_u16mf4_p11_7_not_constant(vuint16mf4_t vs2, _Float16 fs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_fv_se_u16mf4' must be a constant integer}}
|
||||
__riscv_sf_vc_fv_se_u16mf4(p26, index, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_fv_se_u16mf4_p26_overflow(vuint16mf4_t vs2, _Float16 fs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
|
||||
__riscv_sf_vc_fv_se_u16mf4(p26_overflow, p11_7, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_fv_se_u16mf4_p11_7_overflow(vuint16mf4_t vs2, _Float16 fs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 33 is outside the valid range [0, 31]}}
|
||||
__riscv_sf_vc_fv_se_u16mf4(p26, p11_7_overflow, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_vv_se
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_vv_se_u8mf8_p27_26_not_constant(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_vv_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_vv_se_u8mf8(index, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_vv_se_u8mf8_p27_26_overflow(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_vv_se_u8mf8(p27_26_overflow, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_vv
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_vv_u8mf8_p27_26_not_constant(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_vv_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_vv_u8mf8(index, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_vv_u8mf8_p27_26_overflow(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_vv_u8mf8(p27_26_overflow, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_xv_se
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_xv_se_u8mf8_p27_26_not_constant(vuint8mf8_t vs2, uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_xv_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_xv_se_u8mf8(index, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_xv_se_u8mf8_p27_26_overflow(vuint8mf8_t vs2, uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_xv_se_u8mf8(p27_26_overflow, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_xv
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_xv_u8mf8_p27_26_not_constant(vuint8mf8_t vs2, uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_xv_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_xv_u8mf8(index, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_xv_u8mf8_p27_26_overflow(vuint8mf8_t vs2, uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_xv_u8mf8(p27_26_overflow, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_iv_se
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_iv_se_u8mf8_p27_26_not_constant(vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_iv_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_iv_se_u8mf8(index, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_iv_se_u8mf8_simm5_not_constant(vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_iv_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_iv_se_u8mf8(p27_26, vs2, index, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_iv_se_u8mf8_p27_26_overflow(vuint8mf8_t vs2, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_iv_se_u8mf8(p27_26_overflow, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_iv_se_u8mf8_simm5_overflow(vuint8mf8_t vs2, size_t vl) {
|
||||
// expected-error@+1 {{argument value 16 is outside the valid range [-16, 15]}}
|
||||
return __riscv_sf_vc_v_iv_se_u8mf8(p27_26, vs2, simm5_overflow, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_iv
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_iv_u8mf8_p27_26_not_constant(vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_iv_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_iv_u8mf8(index, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_iv_u8mf8_simm5_not_constant(vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_iv_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_iv_u8mf8(p27_26, vs2, index, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_iv_u8mf8_p27_26_overflow(vuint8mf8_t vs2, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_iv_u8mf8(p27_26_overflow, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_iv_u8mf8_simm5_overflow(vuint8mf8_t vs2, size_t vl) {
|
||||
// expected-error@+1 {{argument value 16 is outside the valid range [-16, 15]}}
|
||||
return __riscv_sf_vc_v_iv_u8mf8(p27_26, vs2, simm5_overflow, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_fv_se
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_fv_se_u16mf4_p26_not_constant(vuint16mf4_t vs2, _Float16 fs1, size_t vl, int index) {
|
||||
//expected-error@+1 {{argument to '__riscv_sf_vc_v_fv_se_u16mf4' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_fv_se_u16mf4(index, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_fv_se_u16mf4_p26_overflow(vuint16mf4_t vs2, _Float16 fs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
|
||||
return __riscv_sf_vc_v_fv_se_u16mf4(p26_overflow, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_fv
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_fv_u16mf4_p26_not_constant(vuint16mf4_t vs2, _Float16 fs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_fv_se_u16mf4' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_fv_se_u16mf4(index, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_fv_u16mf4_p26_overflow(vuint16mf4_t vs2, _Float16 fs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
|
||||
return __riscv_sf_vc_v_fv_u16mf4(p26_overflow, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_vvv_se
|
||||
|
||||
void test_sf_vc_vvv_se_u8mf8_p27_26_not_constant(vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_vvv_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_vvv_se_u8mf8(index, vd, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_vvv_se_u8mf8_p27_26_overflow(vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
__riscv_sf_vc_vvv_se_u8mf8(p27_26_overflow, vd, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_xvv_se
|
||||
|
||||
void test_sf_vc_xvv_se_u8mf8_p27_26_not_constant(vuint8mf8_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_xvv_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_xvv_se_u8mf8(index, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_xvv_se_u8mf8_p27_26_overflow(vuint8mf8_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
__riscv_sf_vc_xvv_se_u8mf8(p27_26_overflow, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_ivv_se
|
||||
|
||||
void test_sf_vc_ivv_se_u8mf8_p27_26_not_constant(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_ivv_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_ivv_se_u8mf8(index, vd, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_ivv_se_u8mf8_simm5_not_constant(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_ivv_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_ivv_se_u8mf8(p27_26, vd, vs2, index, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_ivv_se_u8mf8_p27_26_overflow(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
__riscv_sf_vc_ivv_se_u8mf8(p27_26_overflow, vd, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_ivv_se_u8mf8_simm5_overflow(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl) {
|
||||
// expected-error@+1 {{argument value 16 is outside the valid range [-16, 15]}}
|
||||
__riscv_sf_vc_ivv_se_u8mf8(p27_26, vd, vs2, simm5_overflow, vl);
|
||||
}
|
||||
|
||||
// sf_vc_fvv_se
|
||||
|
||||
void test_sf_vc_fvv_se_u16mf4_p26_not_constant(vuint16mf4_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_fvv_se_u16mf4' must be a constant integer}}
|
||||
__riscv_sf_vc_fvv_se_u16mf4(index, vd, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_fvv_se_u16mf4_p26_overflow(vuint16mf4_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
|
||||
__riscv_sf_vc_fvv_se_u16mf4(p26_overflow, vd, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_vvv_se
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_vvv_se_u8mf8_p27_26_not_constant(vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_vvv_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_vvv_se_u8mf8(index, vd, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_vvv_se_u8mf8_p27_26_overflow(vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_vvv_se_u8mf8(p27_26_overflow, vd, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_vvv
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_vvv_u8mf8_p27_26_not_constant(vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_vvv_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_vvv_u8mf8(index, vd, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_vvv_u8mf8_p27_26_overflow(vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_vvv_u8mf8(p27_26_overflow, vd, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_xvv_se
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_xvv_se_u8mf8_p27_26_not_constant(vuint8mf8_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_xvv_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_xvv_se_u8mf8(index, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_xvv_se_u8mf8_p27_26_overflow(vuint8mf8_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_xvv_se_u8mf8(p27_26_overflow, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_xvv
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_xvv_u8mf8_p27_26_not_constant(vuint8mf8_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_xvv_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_xvv_u8mf8(index, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_xvv_u8mf8_p27_26_overflow(vuint8mf8_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_xvv_u8mf8(p27_26_overflow, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_ivv_se
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_ivv_se_u8mf8_p27_26_not_constant(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_ivv_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_ivv_se_u8mf8(index, vd, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_ivv_se_u8mf8_simm5_not_constant(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_ivv_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_ivv_se_u8mf8(p27_26, vd, vs2, index, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_ivv_se_u8mf8_p27_26_overflow(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_ivv_se_u8mf8(p27_26_overflow, vd, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_ivv_se_u8mf8_simm5_overflow(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl) {
|
||||
// expected-error@+1 {{argument value 16 is outside the valid range [-16, 15]}}
|
||||
return __riscv_sf_vc_v_ivv_se_u8mf8(p27_26, vd, vs2, simm5_overflow, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_ivv
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_ivv_u8mf8_p27_26_not_constant(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_ivv_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_ivv_u8mf8(index, vd, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_ivv_u8mf8_simm5_not_constant(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_ivv_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_ivv_u8mf8(p27_26, vd, vs2, index, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_ivv_u8mf8_p27_26_overflow(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_ivv_u8mf8(p27_26_overflow, vd, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
vuint8mf8_t test_sf_vc_v_ivv_u8mf8_simm5_overflow(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl) {
|
||||
// expected-error@+1 {{argument value 16 is outside the valid range [-16, 15]}}
|
||||
return __riscv_sf_vc_v_ivv_u8mf8(p27_26, vd, vs2, simm5_overflow, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_fvv_se
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_fvv_se_u16mf4_p26_not_constant(vuint16mf4_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_fvv_se_u16mf4' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_fvv_se_u16mf4(index, vd, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_fvv_se_u16mf4_p26_overflow(vuint16mf4_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
|
||||
return __riscv_sf_vc_v_fvv_se_u16mf4(p26_overflow, vd, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_fvv
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_fvv_u16mf4_p26_not_constant(vuint16mf4_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_fvv_u16mf4' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_fvv_u16mf4(index, vd, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_fvv_u16mf4_p26_overflow(vuint16mf4_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
|
||||
return __riscv_sf_vc_v_fvv_u16mf4(p26_overflow, vd, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_vvw_se
|
||||
|
||||
void test_sf_vc_vvw_se_u8mf8_p27_26_not_constant(vuint16mf4_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_vvw_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_vvw_se_u8mf8(index, vd, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_vvw_se_u8mf8_p27_26_overflow(vuint16mf4_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
__riscv_sf_vc_vvw_se_u8mf8(p27_26_overflow, vd, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_xvw_se
|
||||
|
||||
void test_sf_vc_xvw_se_u8mf8_p27_26_not_constant(vuint16mf4_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_xvw_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_xvw_se_u8mf8(index, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_xvw_se_u8mf8_p27_26_overflow(vuint16mf4_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
__riscv_sf_vc_xvw_se_u8mf8(p27_26_overflow, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_ivw_se
|
||||
|
||||
void test_sf_vc_ivw_se_u8mf8_p27_26_not_constant(vuint16mf4_t vd, vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_ivw_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_ivw_se_u8mf8(index, vd, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_ivw_se_u8mf8_simm5_not_constant(vuint16mf4_t vd, vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_ivw_se_u8mf8' must be a constant integer}}
|
||||
__riscv_sf_vc_ivw_se_u8mf8(p27_26, vd, vs2, index, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_ivw_se_u8mf8_p27_26_overflow(vuint16mf4_t vd, vuint8mf8_t vs2, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
__riscv_sf_vc_ivw_se_u8mf8(p27_26_overflow, vd, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_ivw_se_u8mf8_simm5_overflow(vuint16mf4_t vd, vuint8mf8_t vs2, size_t vl) {
|
||||
// expected-error@+1 {{argument value 16 is outside the valid range [-16, 15]}}
|
||||
__riscv_sf_vc_ivw_se_u8mf8(p27_26, vd, vs2, simm5_overflow, vl);
|
||||
}
|
||||
|
||||
// sf_vc_fvw_se
|
||||
|
||||
void test_sf_vc_fvw_se_u16mf4_p26_not_constant(vuint32mf2_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_fvw_se_u16mf4' must be a constant integer}}
|
||||
__riscv_sf_vc_fvw_se_u16mf4(index, vd, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
void test_sf_vc_fvw_se_u16mf4_p26_overflow(vuint32mf2_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
|
||||
__riscv_sf_vc_fvw_se_u16mf4(p26_overflow, vd, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_vvw_se
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_vvw_se_u8mf8_p27_26_not_constant(vuint16mf4_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_vvw_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_vvw_se_u8mf8(index, vd, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_vvw_se_u8mf8_p27_26_overflow(vuint16mf4_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_vvw_se_u8mf8(p27_26_overflow, vd, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_vvw
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_vvw_u8mf8_p27_26_not_constant(vuint16mf4_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_vvw_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_vvw_u8mf8(index, vd, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_vvw_u8mf8_p27_26_overflow(vuint16mf4_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_vvw_u8mf8(p27_26_overflow, vd, vs2, vs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_xvw_se
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_xvw_se_u8mf8_p27_26_not_constant(vuint16mf4_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_xvw_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_xvw_se_u8mf8(index, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_xvw_se_u8mf8_p27_26_overflow(vuint16mf4_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_xvw_se_u8mf8(p27_26_overflow, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_xvw
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_xvw_u8mf8_p27_26_not_constant(vuint16mf4_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_xvw_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_xvw_u8mf8(index, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_xvw_u8mf8_p27_26_overflow(vuint16mf4_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_xvw_u8mf8(p27_26_overflow, vd, vs2, rs1, vl);
|
||||
}
|
||||
|
||||
// sf_vc_v_ivw_se
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_ivw_se_u8mf8_p27_26_not_constant(vuint16mf4_t vd, vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_ivw_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_ivw_se_u8mf8(index, vd, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_ivw_se_u8mf8_simm5_not_constant(vuint16mf4_t vd, vuint8mf8_t vs2, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_ivw_se_u8mf8' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_ivw_se_u8mf8(p27_26, vd, vs2, index, vl);
|
||||
}
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_ivw_se_u8mf8_p27_26_overflow(vuint16mf4_t vd, vuint8mf8_t vs2, size_t vl) {
|
||||
// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
|
||||
return __riscv_sf_vc_v_ivw_se_u8mf8(p27_26_overflow, vd, vs2, simm5, vl);
|
||||
}
|
||||
|
||||
vuint16mf4_t test_sf_vc_v_ivw_se_u8mf8_simm5_overflow(vuint16mf4_t vd, vuint8mf8_t vs2, size_t vl) {
|
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// expected-error@+1 {{argument value 16 is outside the valid range [-16, 15]}}
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return __riscv_sf_vc_v_ivw_se_u8mf8(p27_26, vd, vs2, simm5_overflow, vl);
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}
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// sf_vc_v_ivw
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vuint16mf4_t test_sf_vc_v_ivw_u8mf8_p27_26_not_constant(vuint16mf4_t vd, vuint8mf8_t vs2, size_t vl, int index) {
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// expected-error@+1 {{argument to '__riscv_sf_vc_v_ivw_u8mf8' must be a constant integer}}
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return __riscv_sf_vc_v_ivw_u8mf8(index, vd, vs2, simm5, vl);
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}
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vuint16mf4_t test_sf_vc_v_ivw_u8mf8_simm5_not_constant(vuint16mf4_t vd, vuint8mf8_t vs2, size_t vl, int index) {
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// expected-error@+1 {{argument to '__riscv_sf_vc_v_ivw_u8mf8' must be a constant integer}}
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return __riscv_sf_vc_v_ivw_u8mf8(p27_26, vd, vs2, index, vl);
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}
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vuint16mf4_t test_sf_vc_v_ivw_u8mf8_p27_26_overflow(vuint16mf4_t vd, vuint8mf8_t vs2, size_t vl) {
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// expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
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return __riscv_sf_vc_v_ivw_u8mf8(p27_26_overflow, vd, vs2, simm5, vl);
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}
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vuint16mf4_t test_sf_vc_v_ivw_u8mf8_simm5_overflow(vuint16mf4_t vd, vuint8mf8_t vs2, size_t vl) {
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// expected-error@+1 {{argument value 16 is outside the valid range [-16, 15]}}
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return __riscv_sf_vc_v_ivw_u8mf8(p27_26, vd, vs2, simm5_overflow, vl);
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}
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// sf_vc_v_fvw_se
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vuint32mf2_t test_sf_vc_v_fvw_se_u16mf4_p26_not_constant(vuint32mf2_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl, int index) {
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// expected-error@+1 {{argument to '__riscv_sf_vc_v_fvw_se_u16mf4' must be a constant integer}}
|
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return __riscv_sf_vc_v_fvw_se_u16mf4(index, vd, vs2, fs1, vl);
|
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}
|
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|
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vuint32mf2_t test_sf_vc_v_fvw_se_u16mf4_p26_overflow(vuint32mf2_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl) {
|
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// expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
|
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return __riscv_sf_vc_v_fvw_se_u16mf4(p26_overflow, vd, vs2, fs1, vl);
|
||||
}
|
||||
|
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// sf_vc_v_fvw
|
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|
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vuint32mf2_t test_sf_vc_v_fvw_u16mf4_p26_not_constant(vuint32mf2_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl, int index) {
|
||||
// expected-error@+1 {{argument to '__riscv_sf_vc_v_fvw_u16mf4' must be a constant integer}}
|
||||
return __riscv_sf_vc_v_fvw_u16mf4(index, vd, vs2, fs1, vl);
|
||||
}
|
||||
|
||||
vuint32mf2_t test_sf_vc_v_fvw_u16mf4_p26_overflow(vuint32mf2_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl) {
|
||||
// expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
|
||||
return __riscv_sf_vc_v_fvw_u16mf4(p26_overflow, vd, vs2, fs1, vl);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user