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[RISCV][GISel] Add clampScalar G_ZEXTLOAD/G_SEXTLOAD legalization rules.
This fixes i8->i16 on RV32/RV64 and i8/i16/i32->i64 on RV64.
This commit is contained in:
Craig Topper
parent
b8e06933a2
commit
8efd6799f0
@ -119,7 +119,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
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{XLenLLT, p0, s16, 16}});
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if (XLen == 64)
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ExtLoadActions.legalForTypesWithMemDesc({{XLenLLT, p0, s32, 32}});
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ExtLoadActions.lower();
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ExtLoadActions
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.clampScalar(0, s32, XLenLLT)
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.lower();
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getActionDefinitionsBuilder(G_PTR_ADD)
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.legalFor({{p0, XLenLLT}});
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@ -2,6 +2,26 @@
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# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s
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---
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name: zextload_i8_i16
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body: |
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bb.0:
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liveins: $x10
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; CHECK-LABEL: name: zextload_i8_i16
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
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; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
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; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(p0) = COPY $x10
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%2:_(s16) = G_ZEXTLOAD %0(p0) :: (load (s8))
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%3:_(s32) = G_ANYEXT %2(s16)
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$x10 = COPY %3(s32)
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PseudoRET implicit $x10
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...
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---
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name: zextload_i8_i32
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body: |
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@ -39,6 +59,95 @@ body: |
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$x10 = COPY %2(s32)
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PseudoRET implicit $x10
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...
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---
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name: zextload_i8_i64
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body: |
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bb.0:
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liveins: $x10
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; CHECK-LABEL: name: zextload_i8_i64
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
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; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
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; CHECK-NEXT: $x11 = COPY [[C]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
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%0:_(p0) = COPY $x10
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%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s8))
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%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
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$x10 = COPY %3(s32)
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$x11 = COPY %4(s32)
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PseudoRET implicit $x10, implicit $x11
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...
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---
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name: zextload_i16_i64
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body: |
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bb.0:
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liveins: $x10
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; CHECK-LABEL: name: zextload_i16_i64
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
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; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
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; CHECK-NEXT: $x11 = COPY [[C]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
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%0:_(p0) = COPY $x10
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%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s16))
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%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
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$x10 = COPY %3(s32)
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$x11 = COPY %4(s32)
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PseudoRET implicit $x10, implicit $x11
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...
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---
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name: zextload_i32_i64
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body: |
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bb.0:
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liveins: $x10
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; CHECK-LABEL: name: zextload_i32_i64
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: $x10 = COPY [[LOAD]](s32)
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; CHECK-NEXT: $x11 = COPY [[C]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
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%0:_(p0) = COPY $x10
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%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32))
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%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
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$x10 = COPY %3(s32)
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$x11 = COPY %4(s32)
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PseudoRET implicit $x10, implicit $x11
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...
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---
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name: sextload_i8_i16
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body: |
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bb.0:
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liveins: $x10
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; CHECK-LABEL: name: sextload_i8_i16
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
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; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
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; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(p0) = COPY $x10
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%2:_(s16) = G_SEXTLOAD %0(p0) :: (load (s8))
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%3:_(s32) = G_ANYEXT %2(s16)
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$x10 = COPY %3(s32)
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PseudoRET implicit $x10
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...
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---
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name: sextload_i8_i32
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@ -78,3 +187,75 @@ body: |
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PseudoRET implicit $x10
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...
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---
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name: sextload_i8_i64
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body: |
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bb.0:
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liveins: $x10
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; CHECK-LABEL: name: sextload_i8_i64
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
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; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXTLOAD]], [[C]](s32)
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; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
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; CHECK-NEXT: $x11 = COPY [[ASHR]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
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%0:_(p0) = COPY $x10
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%2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s8))
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%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
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$x10 = COPY %3(s32)
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$x11 = COPY %4(s32)
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PseudoRET implicit $x10, implicit $x11
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...
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---
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name: sextload_i16_i64
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body: |
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bb.0:
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liveins: $x10
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; CHECK-LABEL: name: sextload_i16_i64
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
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; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXTLOAD]], [[C]](s32)
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; CHECK-NEXT: $x10 = COPY [[SEXTLOAD]](s32)
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; CHECK-NEXT: $x11 = COPY [[ASHR]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
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%0:_(p0) = COPY $x10
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%2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s16))
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%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
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$x10 = COPY %3(s32)
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$x11 = COPY %4(s32)
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PseudoRET implicit $x10, implicit $x11
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...
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---
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name: sextload_i32_i64
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body: |
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bb.0:
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liveins: $x10
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; CHECK-LABEL: name: sextload_i32_i64
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[C]](s32)
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; CHECK-NEXT: $x10 = COPY [[LOAD]](s32)
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; CHECK-NEXT: $x11 = COPY [[ASHR]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
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%0:_(p0) = COPY $x10
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%2:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32))
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%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
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$x10 = COPY %3(s32)
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$x11 = COPY %4(s32)
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PseudoRET implicit $x10, implicit $x11
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...
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@ -2,6 +2,27 @@
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# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s
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---
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name: zextload_i8_i16
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body: |
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bb.0:
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liveins: $x10
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; CHECK-LABEL: name: zextload_i8_i16
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
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; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD]](s32)
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; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(p0) = COPY $x10
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%2:_(s16) = G_ZEXTLOAD %0(p0) :: (load (s8))
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%3:_(s64) = G_ANYEXT %2(s16)
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$x10 = COPY %3(s64)
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PseudoRET implicit $x10
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...
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---
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name: zextload_i8_i32
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body: |
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@ -100,6 +121,27 @@ body: |
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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---
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name: sextload_i8_i16
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body: |
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bb.0:
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liveins: $x10
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; CHECK-LABEL: name: sextload_i8_i16
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
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; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SEXTLOAD]](s32)
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; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(p0) = COPY $x10
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%2:_(s16) = G_SEXTLOAD %0(p0) :: (load (s8))
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%3:_(s64) = G_ANYEXT %2(s16)
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$x10 = COPY %3(s64)
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PseudoRET implicit $x10
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...
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---
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name: sextload_i8_i32
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