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[SelectionDAG][RISCV] Mask constants to narrow size in TargetLowering::expandUnalignedStore.
If the SRL for Hi constant folds, but we don't remoe those bits from the Lo, we can end up with strange constant folding through DAGCombine later. I've only seen this with constants being lowered to constant pools during lowering on RISC-V.
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@ -9558,6 +9558,14 @@ SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST,
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SDValue ShiftAmount = DAG.getConstant(
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NumBits, dl, getShiftAmountTy(Val.getValueType(), DAG.getDataLayout()));
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SDValue Lo = Val;
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// If Val is a constant, replace the upper bits with 0. The SRL will constant
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// fold and not use the upper bits. A smaller constant may be easier to
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// materialize.
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if (auto *C = dyn_cast<ConstantSDNode>(Lo); C && !C->isOpaque())
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Lo = DAG.getNode(
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ISD::AND, dl, VT, Lo,
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DAG.getConstant(APInt::getLowBitsSet(VT.getSizeInBits(), NumBits), dl,
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VT));
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SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
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// Store the two parts
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@ -416,57 +416,26 @@ define void @merge_stores_i32_i64(ptr %p) {
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ret void
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}
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; FIXME: We shouldn't generate multiple constant pools entries with shifted
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; values.
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;.LCPI0_0:
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; .quad 280223976814164 # 0xfedcba987654
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;.LCPI0_1:
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; .quad 71737338064426034 # 0xfedcba98765432
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;.LCPI0_2:
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; .quad -81985529216486896 # 0xfedcba9876543210
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define void @store_large_constant(ptr %x) {
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; RV32I-LABEL: store_large_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: li a1, 254
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; RV32I-NEXT: sb a1, 7(a0)
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; RV32I-NEXT: li a1, 220
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; RV32I-NEXT: sb a1, 6(a0)
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; RV32I-NEXT: li a1, 186
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; RV32I-NEXT: sb a1, 5(a0)
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; RV32I-NEXT: li a1, 152
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; RV32I-NEXT: sb a1, 4(a0)
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; RV32I-NEXT: li a1, 118
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; RV32I-NEXT: sb a1, 3(a0)
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; RV32I-NEXT: li a1, 84
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; RV32I-NEXT: sb a1, 2(a0)
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; RV32I-NEXT: li a1, 50
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; RV32I-NEXT: sb a1, 1(a0)
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; RV32I-NEXT: li a1, 16
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; RV32I-NEXT: sb a1, 0(a0)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: store_large_constant:
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; RV64I: # %bb.0:
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; RV64I-NEXT: li a1, 254
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; RV64I-NEXT: sb a1, 7(a0)
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; RV64I-NEXT: li a1, 220
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; RV64I-NEXT: sb a1, 6(a0)
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; RV64I-NEXT: li a1, 186
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; RV64I-NEXT: sb a1, 5(a0)
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; RV64I-NEXT: li a1, 152
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; RV64I-NEXT: sb a1, 4(a0)
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; RV64I-NEXT: li a1, 118
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; RV64I-NEXT: lui a2, %hi(.LCPI16_0)
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; RV64I-NEXT: ld a2, %lo(.LCPI16_0)(a2)
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; RV64I-NEXT: lui a3, %hi(.LCPI16_1)
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; RV64I-NEXT: ld a3, %lo(.LCPI16_1)(a3)
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; RV64I-NEXT: lui a4, %hi(.LCPI16_2)
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; RV64I-NEXT: ld a4, %lo(.LCPI16_2)(a4)
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; RV64I-NEXT: sb a1, 3(a0)
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; RV64I-NEXT: sb a2, 2(a0)
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; RV64I-NEXT: sb a3, 1(a0)
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; RV64I-NEXT: sb a4, 0(a0)
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; RV64I-NEXT: ret
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; SLOW-LABEL: store_large_constant:
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; SLOW: # %bb.0:
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; SLOW-NEXT: li a1, 254
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; SLOW-NEXT: sb a1, 7(a0)
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; SLOW-NEXT: li a1, 220
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; SLOW-NEXT: sb a1, 6(a0)
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; SLOW-NEXT: li a1, 186
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; SLOW-NEXT: sb a1, 5(a0)
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; SLOW-NEXT: li a1, 152
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; SLOW-NEXT: sb a1, 4(a0)
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; SLOW-NEXT: li a1, 118
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; SLOW-NEXT: sb a1, 3(a0)
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; SLOW-NEXT: li a1, 84
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; SLOW-NEXT: sb a1, 2(a0)
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; SLOW-NEXT: li a1, 50
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; SLOW-NEXT: sb a1, 1(a0)
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; SLOW-NEXT: li a1, 16
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; SLOW-NEXT: sb a1, 0(a0)
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; SLOW-NEXT: ret
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;
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; RV32I-FAST-LABEL: store_large_constant:
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; RV32I-FAST: # %bb.0:
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