[SelectionDAG][RISCV] Mask constants to narrow size in TargetLowering::expandUnalignedStore.

If the SRL for Hi constant folds, but we don't remoe those bits from
the Lo, we can end up with strange constant folding through DAGCombine later.
I've only seen this with constants being lowered to constant pools
during lowering on RISC-V.
This commit is contained in:
Craig Topper 2023-09-15 19:12:06 -07:00
parent 17a12a27ec
commit 8f04d81ede
2 changed files with 27 additions and 50 deletions

View File

@ -9558,6 +9558,14 @@ SDValue TargetLowering::expandUnalignedStore(StoreSDNode *ST,
SDValue ShiftAmount = DAG.getConstant(
NumBits, dl, getShiftAmountTy(Val.getValueType(), DAG.getDataLayout()));
SDValue Lo = Val;
// If Val is a constant, replace the upper bits with 0. The SRL will constant
// fold and not use the upper bits. A smaller constant may be easier to
// materialize.
if (auto *C = dyn_cast<ConstantSDNode>(Lo); C && !C->isOpaque())
Lo = DAG.getNode(
ISD::AND, dl, VT, Lo,
DAG.getConstant(APInt::getLowBitsSet(VT.getSizeInBits(), NumBits), dl,
VT));
SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
// Store the two parts

View File

@ -416,57 +416,26 @@ define void @merge_stores_i32_i64(ptr %p) {
ret void
}
; FIXME: We shouldn't generate multiple constant pools entries with shifted
; values.
;.LCPI0_0:
; .quad 280223976814164 # 0xfedcba987654
;.LCPI0_1:
; .quad 71737338064426034 # 0xfedcba98765432
;.LCPI0_2:
; .quad -81985529216486896 # 0xfedcba9876543210
define void @store_large_constant(ptr %x) {
; RV32I-LABEL: store_large_constant:
; RV32I: # %bb.0:
; RV32I-NEXT: li a1, 254
; RV32I-NEXT: sb a1, 7(a0)
; RV32I-NEXT: li a1, 220
; RV32I-NEXT: sb a1, 6(a0)
; RV32I-NEXT: li a1, 186
; RV32I-NEXT: sb a1, 5(a0)
; RV32I-NEXT: li a1, 152
; RV32I-NEXT: sb a1, 4(a0)
; RV32I-NEXT: li a1, 118
; RV32I-NEXT: sb a1, 3(a0)
; RV32I-NEXT: li a1, 84
; RV32I-NEXT: sb a1, 2(a0)
; RV32I-NEXT: li a1, 50
; RV32I-NEXT: sb a1, 1(a0)
; RV32I-NEXT: li a1, 16
; RV32I-NEXT: sb a1, 0(a0)
; RV32I-NEXT: ret
;
; RV64I-LABEL: store_large_constant:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 254
; RV64I-NEXT: sb a1, 7(a0)
; RV64I-NEXT: li a1, 220
; RV64I-NEXT: sb a1, 6(a0)
; RV64I-NEXT: li a1, 186
; RV64I-NEXT: sb a1, 5(a0)
; RV64I-NEXT: li a1, 152
; RV64I-NEXT: sb a1, 4(a0)
; RV64I-NEXT: li a1, 118
; RV64I-NEXT: lui a2, %hi(.LCPI16_0)
; RV64I-NEXT: ld a2, %lo(.LCPI16_0)(a2)
; RV64I-NEXT: lui a3, %hi(.LCPI16_1)
; RV64I-NEXT: ld a3, %lo(.LCPI16_1)(a3)
; RV64I-NEXT: lui a4, %hi(.LCPI16_2)
; RV64I-NEXT: ld a4, %lo(.LCPI16_2)(a4)
; RV64I-NEXT: sb a1, 3(a0)
; RV64I-NEXT: sb a2, 2(a0)
; RV64I-NEXT: sb a3, 1(a0)
; RV64I-NEXT: sb a4, 0(a0)
; RV64I-NEXT: ret
; SLOW-LABEL: store_large_constant:
; SLOW: # %bb.0:
; SLOW-NEXT: li a1, 254
; SLOW-NEXT: sb a1, 7(a0)
; SLOW-NEXT: li a1, 220
; SLOW-NEXT: sb a1, 6(a0)
; SLOW-NEXT: li a1, 186
; SLOW-NEXT: sb a1, 5(a0)
; SLOW-NEXT: li a1, 152
; SLOW-NEXT: sb a1, 4(a0)
; SLOW-NEXT: li a1, 118
; SLOW-NEXT: sb a1, 3(a0)
; SLOW-NEXT: li a1, 84
; SLOW-NEXT: sb a1, 2(a0)
; SLOW-NEXT: li a1, 50
; SLOW-NEXT: sb a1, 1(a0)
; SLOW-NEXT: li a1, 16
; SLOW-NEXT: sb a1, 0(a0)
; SLOW-NEXT: ret
;
; RV32I-FAST-LABEL: store_large_constant:
; RV32I-FAST: # %bb.0: