Magic-Mirror/llvm-capstone
1
0
Fork 0
mirror of https://github.com/capstone-engine/llvm-capstone.git synced 2025-02-17 08:21:13 +00:00
Code Issues Actions 3 Packages Projects Releases Wiki Activity

[LV] Widen freeze instead of scalarizing it

Browse Source 
This patch changes the strategy for vectorizing freeze instrucion, from
replicating multiple times to widening according to selected VF.

Fixes #54992

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D125016
This commit is contained in:
lizhijin 2022-05-19 12:20:33 +08:00 committed by zhongyunde
parent 861489af1b
commit 90ea81fcb2
2 changed files with 38 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
View File

@ -8444,6 +8444,7 @@ VPWidenRecipe *VPRecipeBuilder::tryToWiden(Instruction *I,
case Instruction::URem:
case Instruction::Xor:
case Instruction::ZExt:
case Instruction::Freeze:
return true;
}
return false;
@ -9367,6 +9368,17 @@ void VPWidenRecipe::execute(VPTransformState &State) {
break;
}
case Instruction::Freeze: {
State.ILV->setDebugLocFromInst(&I);
for (unsigned Part = 0; Part < State.UF; ++Part) {
Value *Op = State.get(getOperand(0), Part);
Value *Freeze = Builder.CreateFreeze(Op);
State.set(this, Freeze, Part);
}
break;
}
case Instruction::ICmp:
case Instruction::FCmp: {
// Widen compares. Generate vector compares.

26
llvm/test/Transforms/LoopVectorize/vector-freeze.ll Normal file
View File

@ -0,0 +1,26 @@
; RUN: opt -loop-vectorize -force-vector-width=16 -force-vector-interleave=1 -S < %s | FileCheck %s
; RUN: opt -loop-vectorize -scalable-vectorization=on -force-target-supports-scalable-vectors=true -force-vector-width=16 -force-vector-interleave=1 -S < %s | FileCheck %s --check-prefix=SVE
define i64 @test(ptr noalias readonly %addr) {
; CHECK-LABEL: @test(
; CHECK: vector.body:
; CHECK: freeze <16 x i64>
; SVE-LABEL: @test(
; SVE: vector.body:
; SVE: freeze <vscale x 16 x i64>
entry:
br label %loop
exit:
ret i64 %tmp4
loop:
%tmp3 = phi ptr [ %tmp6, %loop ], [ %addr, %entry ]
%tmp4 = freeze i64 0
%tmp5 = add i64 0, 0
%tmp6 = getelementptr inbounds ptr, ptr %tmp3, i64 1
%tmp7 = icmp eq ptr %tmp6, null
br i1 %tmp7, label %exit, label %loop
}