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[AArch64][GlobalISel] Fold G_ADD into the cset for G_ICMP
When we have a G_ADD which is fed by a G_ICMP on one side, we can fold it into the cset for the G_ICMP. e.g. Given ``` %cmp = G_ICMP ... %x, %y %add = G_ADD %cmp, %z ``` We would normally emit a cmp, cset, and add. However, `%add` is either `%z` or `%z + 1`. So, we can just use `%z` as the source of the cset rather than wzr, saving an instruction. This would probably be cleaner in AArch64PostLegalizerLowering, but we'd need to change the way we represent G_ICMP to do that, I think. For now, it's easiest to implement in selection. This is a 0.1% code size improvement on CTMark/pairlocalalign at -Os. Example: https://godbolt.org/z/7KdrP8 Differential Revision: https://reviews.llvm.org/D96388
This commit is contained in:
Jessica Paquette
parent
bda5e57742
commit
9283058abb
@ -252,9 +252,10 @@ private:
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/// Emit a CSet for an integer compare.
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///
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/// \p DefReg is expected to be a 32-bit scalar register.
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/// \p DefReg and \p SrcReg are expected to be 32-bit scalar registers.
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MachineInstr *emitCSetForICMP(Register DefReg, unsigned Pred,
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MachineIRBuilder &MIRBuilder) const;
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MachineIRBuilder &MIRBuilder,
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Register SrcReg = AArch64::WZR) const;
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/// Emit a CSet for a FP compare.
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///
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/// \p Dst is expected to be a 32-bit scalar register.
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@ -2155,6 +2156,41 @@ bool AArch64InstructionSelector::earlySelect(MachineInstr &I) const {
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I.setDesc(TII.get(TargetOpcode::COPY));
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return true;
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}
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case TargetOpcode::G_ADD: {
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// Check if this is being fed by a G_ICMP on either side.
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//
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// (cmp pred, x, y) + z
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//
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// In the above case, when the cmp is true, we increment z by 1. So, we can
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// fold the add into the cset for the cmp by using cinc.
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//
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// FIXME: This would probably be a lot nicer in PostLegalizerLowering.
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Register X = I.getOperand(1).getReg();
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// Only handle scalars. Scalar G_ICMP is only legal for s32, so bail out
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// early if we see it.
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LLT Ty = MRI.getType(X);
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if (Ty.isVector() || Ty.getSizeInBits() != 32)
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return false;
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Register CmpReg = I.getOperand(2).getReg();
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MachineInstr *Cmp = getOpcodeDef(TargetOpcode::G_ICMP, CmpReg, MRI);
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if (!Cmp) {
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std::swap(X, CmpReg);
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Cmp = getOpcodeDef(TargetOpcode::G_ICMP, CmpReg, MRI);
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if (!Cmp)
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return false;
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}
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MachineIRBuilder MIRBuilder(I);
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auto Pred =
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static_cast<CmpInst::Predicate>(Cmp->getOperand(1).getPredicate());
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emitIntegerCompare(Cmp->getOperand(2), Cmp->getOperand(3),
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Cmp->getOperand(1), MIRBuilder);
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emitCSetForICMP(I.getOperand(0).getReg(), Pred, MIRBuilder, X);
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I.eraseFromParent();
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return true;
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}
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default:
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return false;
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}
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@ -4367,14 +4403,13 @@ MachineInstr *AArch64InstructionSelector::emitFMovForFConstant(
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MachineInstr *
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AArch64InstructionSelector::emitCSetForICMP(Register DefReg, unsigned Pred,
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MachineIRBuilder &MIRBuilder) const {
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MachineIRBuilder &MIRBuilder,
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Register SrcReg) const {
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// CSINC increments the result when the predicate is false. Invert it.
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const AArch64CC::CondCode InvCC = changeICMPPredToAArch64CC(
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CmpInst::getInversePredicate((CmpInst::Predicate)Pred));
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auto I =
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MIRBuilder
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.buildInstr(AArch64::CSINCWr, {DefReg}, {Register(AArch64::WZR), Register(AArch64::WZR)})
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.addImm(InvCC);
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auto I = MIRBuilder.buildInstr(AArch64::CSINCWr, {DefReg}, {SrcReg, SrcReg})
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.addImm(InvCC);
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constrainSelectedInstRegOperands(*I, TII, TRI, RBI);
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return &*I;
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}
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@ -270,3 +270,91 @@ body: |
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RET_ReallyLR implicit $w0
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...
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---
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name: cmp_add_rhs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w0, $w1, $w2
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; The CSINC should use the add's RHS.
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; CHECK-LABEL: name: cmp_add_rhs
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; CHECK: liveins: $w0, $w1, $w2
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; CHECK: %cmp_lhs:gpr32 = COPY $w0
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; CHECK: %cmp_rhs:gpr32 = COPY $w1
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; CHECK: %add_rhs:gpr32 = COPY $w2
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; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
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; CHECK: %add:gpr32 = CSINCWr %add_rhs, %add_rhs, 1, implicit $nzcv
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; CHECK: $w0 = COPY %add
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; CHECK: RET_ReallyLR implicit $w0
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%cmp_lhs:gpr(s32) = COPY $w0
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%cmp_rhs:gpr(s32) = COPY $w1
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%add_rhs:gpr(s32) = COPY $w2
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%cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s32), %cmp_rhs
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%add:gpr(s32) = G_ADD %cmp, %add_rhs
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$w0 = COPY %add(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmp_add_lhs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w0, $w1, $w2
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; The CSINC should use the add's LHS.
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; CHECK-LABEL: name: cmp_add_lhs
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; CHECK: liveins: $w0, $w1, $w2
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; CHECK: %cmp_lhs:gpr32 = COPY $w0
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; CHECK: %cmp_rhs:gpr32 = COPY $w1
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; CHECK: %add_lhs:gpr32 = COPY $w2
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; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
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; CHECK: %add:gpr32 = CSINCWr %add_lhs, %add_lhs, 1, implicit $nzcv
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; CHECK: $w0 = COPY %add
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; CHECK: RET_ReallyLR implicit $w0
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%cmp_lhs:gpr(s32) = COPY $w0
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%cmp_rhs:gpr(s32) = COPY $w1
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%add_lhs:gpr(s32) = COPY $w2
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%cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s32), %cmp_rhs
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%add:gpr(s32) = G_ADD %add_lhs, %cmp
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$w0 = COPY %add(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: cmp_add_lhs_vector
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0, $q1, $q2
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; We don't emit CSINC with vectors, so there should be no optimization here.
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; CHECK-LABEL: name: cmp_add_lhs_vector
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; CHECK: liveins: $q0, $q1, $q2
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; CHECK: %cmp_lhs:fpr128 = COPY $q0
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; CHECK: %cmp_rhs:fpr128 = COPY $q1
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; CHECK: %add_lhs:fpr128 = COPY $q2
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; CHECK: [[CMEQv4i32_:%[0-9]+]]:fpr128 = CMEQv4i32 %cmp_lhs, %cmp_rhs
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; CHECK: %add:fpr128 = ADDv4i32 %add_lhs, [[CMEQv4i32_]]
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; CHECK: $q0 = COPY %add
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; CHECK: RET_ReallyLR implicit $q0
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%cmp_lhs:fpr(<4 x s32>) = COPY $q0
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%cmp_rhs:fpr(<4 x s32>) = COPY $q1
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%add_lhs:fpr(<4 x s32>) = COPY $q2
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%cmp:fpr(<4 x s32>) = G_ICMP intpred(eq), %cmp_lhs(<4 x s32>), %cmp_rhs
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%add:fpr(<4 x s32>) = G_ADD %add_lhs, %cmp
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$q0 = COPY %add(<4 x s32>)
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RET_ReallyLR implicit $q0
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