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https://github.com/capstone-engine/llvm-capstone.git
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AMDGPU: Use i16 for i16 shift amount
llvm-svn: 290351
This commit is contained in:
Matt Arsenault
parent
e05e3306a3
commit
941632839f
@ -1811,8 +1811,10 @@ EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
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return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
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}
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MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT) const {
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return MVT::i32;
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MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT VT) const {
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// TODO: Should i16 be used always if legal? For now it would force VALU
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// shifts.
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return (VT == MVT::i16) ? MVT::i16 : MVT::i32;
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}
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// Answering this is somewhat tricky and depends on the specific device which
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@ -416,18 +416,18 @@ def : Pat<
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multiclass Bits_OpsRev_i16_Pats <SDPatternOperator op, Instruction inst> {
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def : Pat<
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(op i16:$src0, i32:$src1),
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(op i16:$src0, i16:$src1),
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(inst $src1, $src0)
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>;
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def : Pat<
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(i32 (zext (op i16:$src0, i32:$src1))),
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(i32 (zext (op i16:$src0, i16:$src1))),
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(inst $src1, $src0)
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>;
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def : Pat<
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(i64 (zext (op i16:$src0, i32:$src1))),
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(i64 (zext (op i16:$src0, i16:$src1))),
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(REG_SEQUENCE VReg_64,
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(inst $src1, $src0), sub0,
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(V_MOV_B32_e32 (i32 0)), sub1)
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@ -464,9 +464,9 @@ def : Pat <
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(V_XOR_B32_e64 $src0, $src1)
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>;
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defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e32>;
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defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e32>;
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defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_I16_e32>;
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defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e64>;
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defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e64>;
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defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_I16_e64>;
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def : ZExt_i16_i1_Pat<zext>;
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def : ZExt_i16_i1_Pat<anyext>;
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@ -19,8 +19,8 @@ declare i32 @llvm.r600.read.tidig.x() #0
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define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32>, <2 x i32> addrspace(1) * %in
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%b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
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%a = load <2 x i32>, <2 x i32> addrspace(1)* %in
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%b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
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%result = shl <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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@ -46,52 +46,102 @@ define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in
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define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32>, <4 x i32> addrspace(1) * %in
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%b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
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%a = load <4 x i32>, <4 x i32> addrspace(1)* %in
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%b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
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%result = shl <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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;VI: {{^}}shl_i16:
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;VI: v_lshlrev_b16_e32 v{{[0-9]+, [0-9]+, [0-9]+}}
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; GCN-LABEL: {{^}}shl_i16:
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; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_lshlrev_b16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define void @shl_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
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%b_ptr = getelementptr i16, i16 addrspace(1)* %in, i16 1
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%a = load i16, i16 addrspace(1) * %in
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%b = load i16, i16 addrspace(1) * %b_ptr
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%a = load i16, i16 addrspace(1)* %in
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%b = load i16, i16 addrspace(1)* %b_ptr
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%result = shl i16 %a, %b
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store i16 %result, i16 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}shl_i16_v_s:
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; VI: v_lshlrev_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}
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;VI: {{^}}shl_v2i16:
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;VI: v_lshlrev_b16_e32 v{{[0-9]+, [0-9]+, [0-9]+}}
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;VI: v_lshlrev_b16_e32 v{{[0-9]+, [0-9]+, [0-9]+}}
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; VI: v_lshlrev_b16_e64 v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}
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define void @shl_i16_v_s(i16 addrspace(1)* %out, i16 addrspace(1)* %in, i16 %b) {
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%a = load i16, i16 addrspace(1)* %in
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%result = shl i16 %a, %b
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store i16 %result, i16 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}shl_i16_v_compute_s:
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; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_lshlrev_b16_e64 v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}
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define void @shl_i16_v_compute_s(i16 addrspace(1)* %out, i16 addrspace(1)* %in, i16 %b) {
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%a = load i16, i16 addrspace(1)* %in
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%b.add = add i16 %b, 3
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%result = shl i16 %a, %b.add
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store i16 %result, i16 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}shl_i16_computed_amount:
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; VI: v_add_u16_e32 [[ADD:v[0-9]+]], 3, v{{[0-9]+}}
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; VI: v_lshlrev_b16_e32 v{{[0-9]+}}, [[ADD]], v{{[0-9]+}}
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define void @shl_i16_computed_amount(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
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%tid = call i32 @llvm.r600.read.tidig.x() #0
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%gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i32 %tid
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%b_ptr = getelementptr i16, i16 addrspace(1)* %gep, i16 1
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%a = load volatile i16, i16 addrspace(1)* %in
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%b = load volatile i16, i16 addrspace(1)* %b_ptr
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%b.add = add i16 %b, 3
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%result = shl i16 %a, %b.add
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store i16 %result, i16 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}shl_i16_i_s:
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; GCN: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 12
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define void @shl_i16_i_s(i16 addrspace(1)* %out, i16 zeroext %a) {
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%result = shl i16 %a, 12
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store i16 %result, i16 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}shl_v2i16:
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; VI: v_lshlrev_b16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_lshlrev_b16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define void @shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in, i16 1
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%a = load <2 x i16>, <2 x i16> addrspace(1) * %in
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%b = load <2 x i16>, <2 x i16> addrspace(1) * %b_ptr
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%tid = call i32 @llvm.r600.read.tidig.x() #0
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%gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
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%b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %gep, i16 1
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%a = load <2 x i16>, <2 x i16> addrspace(1)* %in
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%b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr
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%result = shl <2 x i16> %a, %b
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store <2 x i16> %result, <2 x i16> addrspace(1)* %out
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ret void
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}
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;VI: {{^}}shl_v4i16:
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;VI: v_lshlrev_b16_e32 v{{[0-9]+, [0-9]+, [0-9]+}}
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;VI: v_lshlrev_b16_e32 v{{[0-9]+, [0-9]+, [0-9]+}}
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;VI: v_lshlrev_b16_e32 v{{[0-9]+, [0-9]+, [0-9]+}}
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;VI: v_lshlrev_b16_e32 v{{[0-9]+, [0-9]+, [0-9]+}}
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; GCN-LABEL: {{^}}shl_v4i16:
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; VI: v_lshlrev_b16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_lshlrev_b16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_lshlrev_b16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_lshlrev_b16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define void @shl_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %in, i16 1
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%a = load <4 x i16>, <4 x i16> addrspace(1) * %in
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%b = load <4 x i16>, <4 x i16> addrspace(1) * %b_ptr
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%tid = call i32 @llvm.r600.read.tidig.x() #0
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%gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i32 %tid
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%b_ptr = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %gep, i16 1
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%a = load <4 x i16>, <4 x i16> addrspace(1)* %gep
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%b = load <4 x i16>, <4 x i16> addrspace(1)* %b_ptr
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%result = shl <4 x i16> %a, %b
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store <4 x i16> %result, <4 x i16> addrspace(1)* %out
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store <4 x i16> %result, <4 x i16> addrspace(1)* %gep.out
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ret void
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}
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@ -107,16 +157,13 @@ define void @shl_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in
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;EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
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;EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0
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;SI: {{^}}shl_i64:
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;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;VI: {{^}}shl_i64:
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;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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; GCN-LABEL: {{^}}shl_i64:
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; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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; VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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define void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
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%b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
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%a = load i64, i64 addrspace(1) * %in
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%b = load i64, i64 addrspace(1) * %b_ptr
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%a = load i64, i64 addrspace(1)* %in
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%b = load i64, i64 addrspace(1)* %b_ptr
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%result = shl i64 %a, %b
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store i64 %result, i64 addrspace(1)* %out
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ret void
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@ -154,8 +201,8 @@ define void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
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define void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1
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%a = load <2 x i64>, <2 x i64> addrspace(1) * %in
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%b = load <2 x i64>, <2 x i64> addrspace(1) * %b_ptr
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%a = load <2 x i64>, <2 x i64> addrspace(1)* %in
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%b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr
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%result = shl <2 x i64> %a, %b
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store <2 x i64> %result, <2 x i64> addrspace(1)* %out
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ret void
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@ -217,8 +264,8 @@ define void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in
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define void @shl_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
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%a = load <4 x i64>, <4 x i64> addrspace(1) * %in
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%b = load <4 x i64>, <4 x i64> addrspace(1) * %b_ptr
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%a = load <4 x i64>, <4 x i64> addrspace(1)* %in
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%b = load <4 x i64>, <4 x i64> addrspace(1)* %b_ptr
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%result = shl <4 x i64> %a, %b
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store <4 x i64> %result, <4 x i64> addrspace(1)* %out
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ret void
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