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[LLDB] Add core definition for armv8l and armv7l

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This patch adds core definitions in lldb ArchSpecs for armv8l and armv7l cores.

This was needed because on Linux running on 32-bit Arm v8 we are returned
armv8l in case we are running 32-bit sysroot on 64bit kernel. In case of 32-bit
kernel and 32-bit sysroot running on arm v8 hardware we are returned armv7l.
This is quite common when we run 32 bit arm using docker container.

Signed-off-by: Muhammad Omair Javaid <omair.javaid@linaro.org>

Differential Revision: https://reviews.llvm.org/D69904
This commit is contained in:
Muhammad Omair Javaid 2019-11-13 05:30:25 +05:00
parent 5ad6f279f2
commit 9b95835698
4 changed files with 10 additions and 2 deletions
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2
lldb/include/lldb/Utility/ArchSpec.h
View File

@ -101,6 +101,7 @@ public:
eCore_arm_armv6,
eCore_arm_armv6m,
eCore_arm_armv7,
eCore_arm_armv7l,
eCore_arm_armv7f,
eCore_arm_armv7s,
eCore_arm_armv7k,
@ -122,6 +123,7 @@ public:
eCore_thumbv7em,
eCore_arm_arm64,
eCore_arm_armv8,
eCore_arm_armv8l,
eCore_arm_arm64_32,
eCore_arm_aarch64,

2
lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
View File

@ -25,7 +25,7 @@ def check_first_register_readable(test_case):
if arch in ['x86_64', 'i386']:
test_case.expect("register read eax", substrs=['eax = 0x'])
elif arch in ['arm', 'armv7', 'armv7k']:
elif arch in ['arm', 'armv7', 'armv7k', 'armv8l', 'armv7l']:
test_case.expect("register read r0", substrs=['r0 = 0x'])
elif arch in ['aarch64', 'arm64', 'arm64e', 'arm64_32']:
test_case.expect("register read x0", substrs=['x0 = 0x'])

2
lldb/packages/Python/lldbsuite/test/make/Makefile.rules
View File

@ -239,7 +239,7 @@ else
override ARCH :=
override ARCHFLAG :=
endif
ifeq "$(ARCH)" "arm"
ifeq "$(findstring arm,$(ARCH))" "arm"
override ARCH :=
override ARCHFLAG :=
endif

6
lldb/source/Utility/ArchSpec.cpp
View File

@ -61,6 +61,8 @@ static const CoreDefinition g_core_definitions[] = {
"armv6m"},
{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7,
"armv7"},
{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l,
"armv7l"},
{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f,
"armv7f"},
{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s,
@ -101,6 +103,8 @@ static const CoreDefinition g_core_definitions[] = {
ArchSpec::eCore_arm_arm64, "arm64"},
{eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
ArchSpec::eCore_arm_armv8, "armv8"},
{eByteOrderLittle, 4, 2, 4, llvm::Triple::arm,
ArchSpec::eCore_arm_armv8l, "armv8l"},
{eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32,
ArchSpec::eCore_arm_arm64_32, "arm64_32"},
{eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
@ -1188,6 +1192,8 @@ static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
case ArchSpec::eCore_arm_armv7f:
case ArchSpec::eCore_arm_armv7k:
case ArchSpec::eCore_arm_armv7s:
case ArchSpec::eCore_arm_armv7l:
case ArchSpec::eCore_arm_armv8l:
if (!enforce_exact_match) {
if (core2 == ArchSpec::eCore_arm_generic)
return true;