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[NFC][CodeGen][PPC] Autogenerate checklines in a test to simplify further updates
This commit is contained in:
Roman Lebedev
parent
6ebd16a9ff
commit
9ff087598e
@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -disable-ppc-instr-form-prep=true -mcpu=pwr9 < %s \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck %s -check-prefix=CHECK-P9
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; RUN: llc -verify-machineinstrs -disable-ppc-instr-form-prep=true -mcpu=pwr10 < %s \
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@ -11,29 +12,114 @@ target triple = "powerpc64le-unknown-linux-gnu"
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define void @test(i32* dereferenceable(4) %.ial, i32* noalias dereferenceable(4) %.m, i32* noalias dereferenceable(4) %.n, [0 x %_elem_type_of_a]* %.a, i32* noalias dereferenceable(4) %.lda, [0 x %_elem_type_of_x]* noalias %.x, [0 x %_elem_type_of_y]* noalias %.y) {
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; CHECK-P9-LABEL: test:
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; CHECK-P9: .LBB0_2: # %_loop_2_do_
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; CHECK-P9: lxv vs1, -16(r4)
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; CHECK-P9: lxv vs2, 0(r4)
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; CHECK-P9-DAG: lxv vs3, -16(r3)
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; CHECK-P9-DAG: lxv vs4, 0(r3)
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; CHECK-P9-DAG: xvmaddadp vs1, vs3, vs1
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; CHECK-P9-DAG: stxv vs1, -16(r4)
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; CHECK-P9-DAG: xvmaddadp vs2, vs4, vs0
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; CHECK-P9: stxv vs2, 0(r4)
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; CHECK-P9: bdnz .LBB0_2
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; CHECK-P9: # %bb.0: # %test_entry
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; CHECK-P9-NEXT: andi. r3, r6, 15
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; CHECK-P9-NEXT: lwz r4, 0(r4)
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; CHECK-P9-NEXT: lwz r5, 0(r5)
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; CHECK-P9-NEXT: li r11, 1
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; CHECK-P9-NEXT: addic r3, r3, -1
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; CHECK-P9-NEXT: subfe r10, r3, r3
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; CHECK-P9-NEXT: li r3, 2
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; CHECK-P9-NEXT: not r10, r10
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; CHECK-P9-NEXT: iseleq r3, r11, r3
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; CHECK-P9-NEXT: add r4, r10, r4
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; CHECK-P9-NEXT: srawi r4, r4, 4
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; CHECK-P9-NEXT: addze r4, r4
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; CHECK-P9-NEXT: srawi r5, r5, 1
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; CHECK-P9-NEXT: slwi r4, r4, 4
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; CHECK-P9-NEXT: addze r5, r5
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; CHECK-P9-NEXT: sub r4, r4, r10
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; CHECK-P9-NEXT: cmpw r3, r4
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; CHECK-P9-NEXT: bgtlr cr0
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; CHECK-P9-NEXT: # %bb.1: # %_loop_2_do_.lr.ph
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; CHECK-P9-NEXT: extswsli r5, r5, 3
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; CHECK-P9-NEXT: extsw r10, r4
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; CHECK-P9-NEXT: add r5, r8, r5
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; CHECK-P9-NEXT: clrldi r8, r3, 32
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; CHECK-P9-NEXT: lwa r3, 0(r7)
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; CHECK-P9-NEXT: addi r4, r8, 1
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; CHECK-P9-NEXT: addi r5, r5, -8
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; CHECK-P9-NEXT: lxvdsx vs0, 0, r5
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; CHECK-P9-NEXT: sub r3, r4, r3
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; CHECK-P9-NEXT: sldi r4, r4, 3
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; CHECK-P9-NEXT: sldi r3, r3, 3
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; CHECK-P9-NEXT: add r4, r9, r4
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; CHECK-P9-NEXT: add r3, r6, r3
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; CHECK-P9-NEXT: sub r6, r10, r8
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; CHECK-P9-NEXT: rldicl r6, r6, 60, 4
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; CHECK-P9-NEXT: addi r6, r6, 1
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; CHECK-P9-NEXT: mtctr r6
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; CHECK-P9-NEXT: .p2align 4
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; CHECK-P9-NEXT: .LBB0_2: # %_loop_2_do_
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; CHECK-P9-NEXT: #
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; CHECK-P9-NEXT: lxv vs1, -16(r4)
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; CHECK-P9-NEXT: lxv vs2, 0(r4)
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; CHECK-P9-NEXT: lxv vs3, -16(r3)
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; CHECK-P9-NEXT: lxv vs4, 0(r3)
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; CHECK-P9-NEXT: addi r3, r3, 128
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; CHECK-P9-NEXT: xvmaddadp vs1, vs3, vs1
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; CHECK-P9-NEXT: stxv vs1, -16(r4)
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; CHECK-P9-NEXT: xvmaddadp vs2, vs4, vs0
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; CHECK-P9-NEXT: stxv vs2, 0(r4)
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; CHECK-P9-NEXT: addi r4, r4, 128
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; CHECK-P9-NEXT: bdnz .LBB0_2
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; CHECK-P9-NEXT: # %bb.3: # %_return_bb
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; CHECK-P9-NEXT: blr
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;
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; FIXME: use pair load/store instructions lxvp/stxvp
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; CHECK-P10-LABEL: test:
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; CHECK-P10: .LBB0_2: # %_loop_2_do_
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; CHECK-P10: lxv vs1, -16(r4)
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; CHECK-P10: lxv vs2, 0(r4)
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; CHECK-P10-DAG: lxv vs3, -16(r3)
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; CHECK-P10-DAG: lxv vs4, 0(r3)
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; CHECK-P10-DAG: xvmaddadp vs1, vs3, vs1
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; CHECK-P10-DAG: xvmaddadp vs2, vs4, vs0
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; CHECK-P10-DAG: stxv vs1, -16(r4)
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; CHECK-P10: stxv vs2, 0(r4)
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; CHECK-P10: bdnz .LBB0_2
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; CHECK-P10: # %bb.0: # %test_entry
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; CHECK-P10-NEXT: lwz r4, 0(r4)
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; CHECK-P10-NEXT: andi. r3, r6, 15
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; CHECK-P10-NEXT: li r3, 2
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; CHECK-P10-NEXT: li r10, 1
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; CHECK-P10-NEXT: lwz r5, 0(r5)
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; CHECK-P10-NEXT: iseleq r3, r10, r3
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; CHECK-P10-NEXT: setnbc r10, eq
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; CHECK-P10-NEXT: not r10, r10
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; CHECK-P10-NEXT: add r4, r10, r4
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; CHECK-P10-NEXT: srawi r4, r4, 4
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; CHECK-P10-NEXT: addze r4, r4
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; CHECK-P10-NEXT: srawi r5, r5, 1
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; CHECK-P10-NEXT: slwi r4, r4, 4
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; CHECK-P10-NEXT: addze r5, r5
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; CHECK-P10-NEXT: sub r4, r4, r10
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; CHECK-P10-NEXT: cmpw r3, r4
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; CHECK-P10-NEXT: bgtlr cr0
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; CHECK-P10-NEXT: # %bb.1: # %_loop_2_do_.lr.ph
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; CHECK-P10-NEXT: extswsli r5, r5, 3
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; CHECK-P10-NEXT: extsw r10, r4
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; CHECK-P10-NEXT: add r5, r8, r5
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; CHECK-P10-NEXT: clrldi r8, r3, 32
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; CHECK-P10-NEXT: lwa r3, 0(r7)
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; CHECK-P10-NEXT: addi r4, r8, 1
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; CHECK-P10-NEXT: addi r5, r5, -8
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; CHECK-P10-NEXT: lxvdsx vs0, 0, r5
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; CHECK-P10-NEXT: sub r3, r4, r3
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; CHECK-P10-NEXT: sldi r4, r4, 3
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; CHECK-P10-NEXT: add r4, r9, r4
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; CHECK-P10-NEXT: sldi r3, r3, 3
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; CHECK-P10-NEXT: add r3, r6, r3
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; CHECK-P10-NEXT: sub r6, r10, r8
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; CHECK-P10-NEXT: rldicl r6, r6, 60, 4
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; CHECK-P10-NEXT: addi r6, r6, 1
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; CHECK-P10-NEXT: mtctr r6
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; CHECK-P10-NEXT: .p2align 4
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; CHECK-P10-NEXT: .LBB0_2: # %_loop_2_do_
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; CHECK-P10-NEXT: #
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; CHECK-P10-NEXT: lxv vs1, -16(r4)
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; CHECK-P10-NEXT: lxv vs2, 0(r4)
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; CHECK-P10-NEXT: lxv vs3, -16(r3)
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; CHECK-P10-NEXT: xvmaddadp vs1, vs3, vs1
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; CHECK-P10-NEXT: lxv vs4, 0(r3)
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; CHECK-P10-NEXT: xvmaddadp vs2, vs4, vs0
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; CHECK-P10-NEXT: addi r3, r3, 128
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; CHECK-P10-NEXT: stxv vs1, -16(r4)
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; CHECK-P10-NEXT: stxv vs2, 0(r4)
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; CHECK-P10-NEXT: addi r4, r4, 128
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; CHECK-P10-NEXT: bdnz .LBB0_2
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; CHECK-P10-NEXT: # %bb.3: # %_return_bb
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; CHECK-P10-NEXT: blr
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; FIXME: use pair load/store instructions lxvp/stxvp
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test_entry:
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%_conv5 = ptrtoint [0 x %_elem_type_of_a]* %.a to i64
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%_andi_tmp = and i64 %_conv5, 15
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