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[X86][ZnVer1] Cleanup more single match instregexs
llvm-svn: 332712
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@ -942,19 +942,23 @@ def ZnWriteFPUY : SchedWriteRes<[ZnFPU]> {
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// MOVD.
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// r32/64 <- (x)mm.
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def : InstRW<[ZnWriteToALU2], (instregex "MMX_MOVD64grr", "MMX_MOVD64from64rr",
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"VMOVPDI2DIrr", "MOVPDI2DIrr")>;
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def : InstRW<[ZnWriteToALU2], (instrs MMX_MOVD64grr,
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MMX_MOVD64from64rr,
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MOVPDI2DIrr,
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VMOVPDI2DIrr)>;
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// (x)mm <- r32/64.
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def : InstRW<[ZnWriteFPU2], (instregex "MMX_MOVD64rr", "MMX_MOVD64to64rr",
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"VMOVDI2PDIrr", "MOVDI2PDIrr")>;
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def : InstRW<[ZnWriteFPU2], (instrs MMX_MOVD64rr,
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MMX_MOVD64to64rr,
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MOVDI2PDIrr,
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VMOVDI2PDIrr)>;
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// MOVQ.
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// r64 <- (x)mm.
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def : InstRW<[ZnWriteToALU2], (instregex "VMOVPQIto64rr")>;
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def : InstRW<[ZnWriteToALU2], (instrs VMOVPQIto64rr)>;
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// (x)mm <- r64.
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def : InstRW<[ZnWriteFPU2], (instregex "VMOV64toPQIrr")>;
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def : InstRW<[ZnWriteFPU2], (instrs VMOV64toPQIrr)>;
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// (x)mm <- (x)mm.
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def : InstRW<[ZnWriteFPU], (instregex "MMX_MOVQ64rr")>;
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@ -975,10 +979,12 @@ def ZnWriteFPU12Ym : SchedWriteRes<[ZnAGU, ZnFPU12]> {
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let NumMicroOps = 2;
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}
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def : InstRW<[ZnWriteFPU12], (instregex "MMX_PACKSSDWirr",
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"MMX_PACKSSWBirr", "MMX_PACKUSWBirr")>;
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def : InstRW<[ZnWriteFPU12m], (instregex "MMX_PACKSSDWirm",
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"MMX_PACKSSWBirm", "MMX_PACKUSWBirm")>;
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def : InstRW<[ZnWriteFPU12], (instrs MMX_PACKSSDWirr,
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MMX_PACKSSWBirr,
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MMX_PACKUSWBirr)>;
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def : InstRW<[ZnWriteFPU12m], (instrs MMX_PACKSSDWirm,
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MMX_PACKSSWBirm,
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MMX_PACKUSWBirm)>;
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// VPMOVSX/ZX BW BD BQ WD WQ DQ.
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// y <- x.
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@ -1006,12 +1012,12 @@ def ZnWriteFPU013LdY : SchedWriteRes<[ZnAGU, ZnFPU013]> {
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// x,x,i / v,v,v,i
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def : InstRW<[ZnWriteFPU013], (instregex "(V?)PBLENDWrri")>;
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// ymm
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def : InstRW<[ZnWriteFPU013Y], (instregex "(V?)PBLENDWYrri")>;
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def : InstRW<[ZnWriteFPU013Y], (instrs VPBLENDWYrri)>;
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// x,m,i / v,v,m,i
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def : InstRW<[ZnWriteFPU013Ld], (instregex "(V?)PBLENDWrmi")>;
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// y,m,i
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def : InstRW<[ZnWriteFPU013LdY], (instregex "(V?)PBLENDWYrmi")>;
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def : InstRW<[ZnWriteFPU013LdY], (instrs VPBLENDWYrmi)>;
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def ZnWriteFPU01 : SchedWriteRes<[ZnFPU01]> ;
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def ZnWriteFPU01Y : SchedWriteRes<[ZnFPU01]> {
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@ -1020,9 +1026,9 @@ def ZnWriteFPU01Y : SchedWriteRes<[ZnFPU01]> {
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// VPBLENDD.
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// v,v,v,i.
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def : InstRW<[ZnWriteFPU01], (instregex "VPBLENDDrri")>;
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def : InstRW<[ZnWriteFPU01], (instrs VPBLENDDrri)>;
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// ymm
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def : InstRW<[ZnWriteFPU01Y], (instregex "VPBLENDDYrri")>;
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def : InstRW<[ZnWriteFPU01Y], (instrs VPBLENDDYrri)>;
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// v,v,m,i
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def ZnWriteFPU01Op2 : SchedWriteRes<[ZnAGU, ZnFPU01]> {
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@ -1035,8 +1041,8 @@ def ZnWriteFPU01Op2Y : SchedWriteRes<[ZnAGU, ZnFPU01]> {
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let Latency = 9;
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let ResourceCycles = [1, 3];
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}
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def : InstRW<[ZnWriteFPU01Op2], (instregex "VPBLENDDrmi")>;
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def : InstRW<[ZnWriteFPU01Op2Y], (instregex "VPBLENDDYrmi")>;
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def : InstRW<[ZnWriteFPU01Op2], (instrs VPBLENDDrmi)>;
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def : InstRW<[ZnWriteFPU01Op2Y], (instrs VPBLENDDYrmi)>;
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// MASKMOVQ.
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def : InstRW<[WriteMicrocoded], (instregex "MMX_MASKMOVQ(64)?")>;
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@ -1099,7 +1105,7 @@ def ZnWritePCMPGTQYm : SchedWriteRes<[ZnAGU, ZnFPU03]> {
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let ResourceCycles = [1,2];
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}
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def : InstRW<[ZnWritePCMPGTQm], (instregex "(V?)PCMPGTQrm")>;
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def : InstRW<[ZnWritePCMPGTQYm], (instregex "(V?)PCMPGTQYrm")>;
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def : InstRW<[ZnWritePCMPGTQYm], (instrs VPCMPGTQYrm)>;
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//-- Logic instructions --//
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@ -1118,15 +1124,15 @@ def : InstRW<[ZnWritePShiftY], (instregex "(V?)PS(R|L)LDQYri")>;
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//-- Move instructions --//
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// VPERM2F128.
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def : InstRW<[WriteMicrocoded], (instregex "VPERM2F128rr")>;
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def : InstRW<[WriteMicrocoded], (instregex "VPERM2F128rm")>;
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def : InstRW<[WriteMicrocoded], (instrs VPERM2F128rr)>;
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def : InstRW<[WriteMicrocoded], (instrs VPERM2F128rm)>;
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def ZnWriteBROADCAST : SchedWriteRes<[ZnAGU, ZnFPU13]> {
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let NumMicroOps = 2;
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let Latency = 8;
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}
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// VBROADCASTF128.
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def : InstRW<[ZnWriteBROADCAST], (instregex "VBROADCASTF128")>;
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def : InstRW<[ZnWriteBROADCAST], (instrs VBROADCASTF128)>;
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// EXTRACTPS.
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// r32,x,i.
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@ -1147,10 +1153,10 @@ def : InstRW<[ZnWriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
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// VEXTRACTF128.
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// x,y,i.
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def : InstRW<[ZnWriteFPU013], (instregex "VEXTRACTF128rr")>;
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def : InstRW<[ZnWriteFPU013], (instrs VEXTRACTF128rr)>;
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// m128,y,i.
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def : InstRW<[ZnWriteFPU013m], (instregex "VEXTRACTF128mr")>;
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def : InstRW<[ZnWriteFPU013m], (instrs VEXTRACTF128mr)>;
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def ZnWriteVINSERT128r: SchedWriteRes<[ZnFPU013]> {
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let Latency = 2;
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@ -1163,35 +1169,11 @@ def ZnWriteVINSERT128Ld: SchedWriteRes<[ZnAGU,ZnFPU013]> {
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}
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// VINSERTF128.
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// y,y,x,i.
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def : InstRW<[ZnWriteVINSERT128r], (instregex "VINSERTF128rr")>;
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def : InstRW<[ZnWriteVINSERT128Ld], (instregex "VINSERTF128rm")>;
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def : InstRW<[ZnWriteVINSERT128r], (instrs VINSERTF128rr)>;
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def : InstRW<[ZnWriteVINSERT128Ld], (instrs VINSERTF128rm)>;
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// VGATHERDPS.
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// x.
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def : InstRW<[WriteMicrocoded], (instregex "VGATHERDPSrm")>;
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// y.
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def : InstRW<[WriteMicrocoded], (instregex "VGATHERDPSYrm")>;
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// VGATHERQPS.
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// x.
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def : InstRW<[WriteMicrocoded], (instregex "VGATHERQPSrm")>;
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// y.
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def : InstRW<[WriteMicrocoded], (instregex "VGATHERQPSYrm")>;
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// VGATHERDPD.
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// x.
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def : InstRW<[WriteMicrocoded], (instregex "VGATHERDPDrm")>;
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// y.
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def : InstRW<[WriteMicrocoded], (instregex "VGATHERDPDYrm")>;
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// VGATHERQPD.
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// x.
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def : InstRW<[WriteMicrocoded], (instregex "VGATHERQPDrm")>;
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// y.
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def : InstRW<[WriteMicrocoded], (instregex "VGATHERQPDYrm")>;
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// VGATHER.
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def : InstRW<[WriteMicrocoded], (instregex "VGATHER(Q|D)(PD|PS)(Y?)rm")>;
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//-- Conversion instructions --//
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def ZnWriteCVTPD2PSr: SchedWriteRes<[ZnFPU3]> {
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@ -1276,7 +1258,7 @@ def : InstRW<[ZnWriteCVTDQ2PDr], (instregex "(V)?CVTDQ2PDrr")>;
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// Same as xmm
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// y,x.
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def : InstRW<[ZnWriteCVTDQ2PDr], (instregex "VCVTDQ2PDYrr")>;
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def : InstRW<[ZnWriteCVTDQ2PDr], (instrs VCVTDQ2PDYrr)>;
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def ZnWriteCVTPD2DQr: SchedWriteRes<[ZnFPU12, ZnFPU3]> {
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let Latency = 5;
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@ -1306,7 +1288,7 @@ def : InstRW<[ZnWriteCVTPS2PIr], (instregex "MMX_CVT(T?)PS2PIirr")>;
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// CVTPI2PD.
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// x,mm.
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def : InstRW<[ZnWriteCVTPS2PDr], (instregex "MMX_CVTPI2PDirr")>;
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def : InstRW<[ZnWriteCVTPS2PDr], (instrs MMX_CVTPI2PDirr)>;
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// CVT(T)PD2PI.
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// mm,x.
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