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https://github.com/capstone-engine/llvm-capstone.git
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Remove branching instructions which are actually alias.
This commit is contained in:
Rot127
Rot127
parent
0162e01063
commit
a3cc36f886
@ -311,11 +311,8 @@ def : InstRW<[P10W_BF_7C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY],
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def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read],
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(instrs
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B, BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCCLRL, CTRL_DEP, TAILB, TAILB8,
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BA, TAILBA, TAILBA8,
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BCCTR, BCCTR8, BCCTR8n, BCCTRn, gBCCTR,
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BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, gBCCTRL,
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BCLR, BCLRn, BDNZLR, BDNZLR8, BDNZLRm, BDNZLRp, BDZLR, BDZLR8, BDZLRm, BDZLRp, gBCLR,
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BCLRL, BCLRLn, BDNZLRL, BDNZLRLm, BDNZLRLp, BDZLRL, BDZLRLm, BDZLRLp, gBCLRL,
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BA, TAILBA, TAILBA8, BCCTR, BCCTR8, gBCCTR,
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BCCTRL, BCCTRL8, gBCCTRL, BCLR, gBCLR, BCLRL, gBCLRL,
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BL, BL8, BL8_NOP, BL8_NOP_RM, BL8_NOP_TLS, BL8_NOTOC, BL8_NOTOC_RM, BL8_NOTOC_TLS, BL8_RM, BL8_TLS, BL8_TLS_, BLR, BLR8, BLRL, BL_NOP, BL_NOP_RM, BL_RM, BL_TLS,
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BLA, BLA8, BLA8_NOP, BLA8_NOP_RM, BLA8_RM, BLA_RM
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)>;
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@ -323,10 +320,8 @@ def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read],
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// 2 Cycles Branch operations, 2 input operands
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def : InstRW<[P10W_BR_2C, P10W_DISP_ANY, P10BR_Read, P10BR_Read],
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(instrs
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BC, BCTR, BCTR8, BCTRL, BCTRL8, BCTRL8_LDinto_toc, BCTRL8_LDinto_toc_RM, BCTRL8_RM, BCTRL_LWZinto_toc, BCTRL_LWZinto_toc_RM, BCTRL_RM, BCn, BDNZ, BDNZ8, BDNZm, BDNZp, BDZ, BDZ8, BDZm, BDZp, TAILBCTR, TAILBCTR8, gBC, gBCat,
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BDNZA, BDNZAm, BDNZAp, BDZA, BDZAm, BDZAp, gBCA, gBCAat,
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BCL, BCLalways, BCLn, BDNZL, BDNZLm, BDNZLp, BDZL, BDZLm, BDZLp, gBCL, gBCLat,
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BDNZLA, BDNZLAm, BDNZLAp, BDZLA, BDZLAm, BDZLAp, gBCLA, gBCLAat
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BC, BCTR, BCTR8, BCTRL, BCTRL8, BCTRL8_LDinto_toc, BCTRL8_LDinto_toc_RM, BCTRL8_RM, BCTRL_LWZinto_toc, BCTRL_LWZinto_toc_RM, BCTRL_RM, TAILBCTR, TAILBCTR8, gBC, gBCat,
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gBCA, gBCAat, BCL, gBCL, gBCLat, gBCLA, gBCLAat
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)>;
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// 7 Cycles Crypto operations, 1 input operands
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@ -1299,8 +1299,6 @@ def : InstRW<[P9_BR_2C, DISP_BR_1C],
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(instregex "BCCCTR(L)?(8)?$"),
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(instregex "BCCL(A|R|RL)?$"),
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(instregex "BCCTR(L)?(8)?(n)?$"),
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(instregex "BD(N)?Z(8|A|Am|Ap|m|p)?$"),
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(instregex "BD(N)?ZL(A|Am|Ap|R|R8|RL|RLm|RLp|Rm|Rp|m|p)?$"),
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(instregex "BL(_TLS|_NOP)?(_RM)?$"),
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(instregex "BL8(_TLS|_NOP|_NOP_TLS|_TLS_)?(_RM)?$"),
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(instregex "BLA(8|8_NOP)?(_RM)?$"),
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@ -1316,13 +1314,10 @@ def : InstRW<[P9_BR_2C, DISP_BR_1C],
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BCC,
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BCCA,
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BCL,
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BCLalways,
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BCLn,
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BCTRL8_LDinto_toc,
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BCTRL_LWZinto_toc,
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BCTRL8_LDinto_toc_RM,
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BCTRL_LWZinto_toc_RM,
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BCn,
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CTRL_DEP
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)>;
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@ -90,9 +90,6 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
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def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI),
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"bcctr 12, $BI, 0", IIC_BrB, []>,
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Requires<[In64BitMode]>;
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def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI),
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"bcctr 4, $BI, 0", IIC_BrB, []>,
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Requires<[In64BitMode]>;
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}
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}
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@ -100,24 +97,6 @@ let Defs = [LR8] in
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def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>,
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PPC970_Unit_BRU;
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let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
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let Defs = [CTR8], Uses = [CTR8] in {
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def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD),
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"bdz $BD">;
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def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD),
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"bdnz $BD">;
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}
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let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
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def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
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"bdzlr", IIC_BrB, []>;
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def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
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"bdnzlr", IIC_BrB, []>;
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}
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}
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let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in {
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// Convenient aliases for call instructions
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let Uses = [RM] in {
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@ -171,9 +150,6 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in {
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def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI),
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"bcctrl 12, $BI, 0", IIC_BrB, []>,
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Requires<[In64BitMode]>;
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def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI),
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"bcctrl 4, $BI, 0", IIC_BrB, []>,
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Requires<[In64BitMode]>;
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}
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}
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}
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@ -1337,8 +1337,6 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in {
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def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI),
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"bcctr 12, $BI, 0", IIC_BrB, []>;
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def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI),
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"bcctr 4, $BI, 0", IIC_BrB, []>;
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}
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}
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}
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@ -1402,68 +1400,11 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
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def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD),
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"bc 12, $BI, $BD">;
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let Pattern = [(brcond (not i1:$BI), bb:$BD)] in
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def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD),
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"bc 4, $BI, $BD">;
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let isReturn = 1, Uses = [LR, RM] in {
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def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$BI),
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"bclr 12, $BI, 0", IIC_BrB, []>;
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def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$BI),
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"bclr 4, $BI, 0", IIC_BrB, []>;
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}
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}
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let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
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def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
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"bdzlr", IIC_BrB, []>;
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def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
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"bdnzlr", IIC_BrB, []>;
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def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
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"bdzlr+", IIC_BrB, []>;
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def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
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"bdnzlr+", IIC_BrB, []>;
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def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
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"bdzlr-", IIC_BrB, []>;
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def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
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"bdnzlr-", IIC_BrB, []>;
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}
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let Defs = [CTR], Uses = [CTR] in {
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def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD),
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"bdz $BD">;
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def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD),
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"bdnz $BD">;
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def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$BD),
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"bdza $BD">;
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def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$BD),
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"bdnza $BD">;
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def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$BD),
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"bdz+ $BD">;
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def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$BD),
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"bdnz+ $BD">;
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def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$BD),
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"bdza+ $BD">;
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def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$BD),
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"bdnza+ $BD">;
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def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$BD),
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"bdz- $BD">;
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def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$BD),
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"bdnz- $BD">;
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def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$BD),
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"bdza- $BD">;
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def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$BD),
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"bdnza- $BD">;
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}
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}
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// The unconditional BCL used by the SjLj setjmp code.
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let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7,
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hasSideEffects = 0 in {
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let Defs = [LR], Uses = [RM] in {
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def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$BD),
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"bcl 20, 31, $BD">;
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}
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}
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let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
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@ -1485,9 +1426,6 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
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def BCL : BForm_4<16, 12, 0, 1, (outs),
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(ins crbitrc:$BI, condbrtarget:$BD),
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"bcl 12, $BI, $BD">;
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def BCLn : BForm_4<16, 4, 0, 1, (outs),
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(ins crbitrc:$BI, condbrtarget:$BD),
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"bcl 4, $BI, $BD">;
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def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
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(outs), (ins calltarget:$LI),
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"bl $LI\n\tnop", IIC_BrB, []>;
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@ -1506,8 +1444,6 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
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def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI),
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"bcctrl 12, $BI, 0", IIC_BrB, []>;
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def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI),
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"bcctrl 4, $BI, 0", IIC_BrB, []>;
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}
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}
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let Uses = [LR, RM] in {
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@ -1521,50 +1457,8 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
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def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$BI),
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"bclrl 12, $BI, 0", IIC_BrB, []>;
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def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$BI),
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"bclrl 4, $BI, 0", IIC_BrB, []>;
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}
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}
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let Defs = [CTR], Uses = [CTR, RM] in {
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def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$BD),
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"bdzl $BD">;
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def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$BD),
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"bdnzl $BD">;
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def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$BD),
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"bdzla $BD">;
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def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$BD),
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"bdnzla $BD">;
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def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$BD),
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"bdzl+ $BD">;
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def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$BD),
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"bdnzl+ $BD">;
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def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$BD),
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"bdzla+ $BD">;
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def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$BD),
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"bdnzla+ $BD">;
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def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$BD),
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"bdzl- $BD">;
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def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$BD),
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"bdnzl- $BD">;
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def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$BD),
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"bdzla- $BD">;
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def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$BD),
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"bdnzla- $BD">;
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}
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let Defs = [CTR], Uses = [CTR, LR, RM] in {
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def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
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"bdzlrl", IIC_BrB, []>;
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def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
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"bdnzlrl", IIC_BrB, []>;
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def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
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"bdzlrl+", IIC_BrB, []>;
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def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
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"bdnzlrl+", IIC_BrB, []>;
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def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
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"bdzlrl-", IIC_BrB, []>;
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def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
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"bdnzlrl-", IIC_BrB, []>;
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}
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}
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let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in {
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@ -4947,11 +4841,6 @@ multiclass BranchSimpleMnemonicAT<string pm, int at> {
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defm : BranchSimpleMnemonicAT<"+", 3>;
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defm : BranchSimpleMnemonicAT<"-", 2>;
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def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
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def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
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def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
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def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
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multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
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def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
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def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
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@ -4960,22 +4849,64 @@ multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
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def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
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def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
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}
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/// No CTR decement, check CR T/F, branch to CTR, save/don't save LR
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multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
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: BranchSimpleMnemonic1<name, pm, bo> {
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def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
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def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
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}
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/// CTR decrement, no CR check, branch to LR, save/don't save LR
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multiclass BranchSimpleMnemonic3<string name, string pm, int bo> {
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def : InstAlias<"b"#name#"lr"#pm, (gBCLR bo, CR0LT, 0)>;
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def : InstAlias<"b"#name#"lrl"#pm, (gBCLRL bo, CR0LT, 0)>;
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}
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/// CTR decrement, no CR check, save/don't save LR, branch relative/absolute alias.
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multiclass BranchSimpleMnemonic4<string name, string pm, int at, int bo> {
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def : InstAlias<"b"#name#"l"#pm#" $dst", (gBCLat bo, at, CR0LT, condbrtarget:$dst)>;
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def : InstAlias<"b"#name#"la"#pm#" $dst", (gBCLAat bo, at, CR0LT, abscondbrtarget:$dst)>;
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def : InstAlias<"b"#name#""#pm#" $dst", (gBCat bo, at, CR0LT, condbrtarget:$dst)>;
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def : InstAlias<"b"#name#""#pm#" $dst", (gBCAat bo, at, CR0LT, abscondbrtarget:$dst)>;
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}
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defm : BranchSimpleMnemonic4<"dz", "", 0, 18>;
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defm : BranchSimpleMnemonic4<"dnz", "", 0, 16>;
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defm : BranchSimpleMnemonic4<"dz", "+", 3, 27>;
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defm : BranchSimpleMnemonic4<"dnz", "+", 3, 25>;
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defm : BranchSimpleMnemonic4<"dz", "-", 2, 26>;
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defm : BranchSimpleMnemonic4<"dnz", "-", 2, 24>;
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defm : BranchSimpleMnemonic3<"dz", "", 18>;
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defm : BranchSimpleMnemonic3<"dnz", "", 16>;
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||||
defm : BranchSimpleMnemonic3<"dz", "+", 27>;
|
||||
defm : BranchSimpleMnemonic3<"dnz", "+", 25>;
|
||||
defm : BranchSimpleMnemonic3<"dz", "-", 26>;
|
||||
defm : BranchSimpleMnemonic3<"dnz", "-", 24>;
|
||||
|
||||
defm : BranchSimpleMnemonic2<"t", "", 12>;
|
||||
defm : BranchSimpleMnemonic2<"f", "", 4>;
|
||||
defm : BranchSimpleMnemonic2<"t", "-", 14>;
|
||||
defm : BranchSimpleMnemonic2<"f", "-", 6>;
|
||||
defm : BranchSimpleMnemonic2<"t", "+", 15>;
|
||||
defm : BranchSimpleMnemonic2<"f", "+", 7>;
|
||||
|
||||
defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
|
||||
defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
|
||||
defm : BranchSimpleMnemonic1<"dzt", "", 10>;
|
||||
defm : BranchSimpleMnemonic1<"dzf", "", 2>;
|
||||
|
||||
/// Conditional branches which branch always
|
||||
def : InstAlias<"b $dst", (gBC 20, CR0LT, condbrtarget:$dst)>;
|
||||
def : InstAlias<"ba $dst", (gBCA 20, CR0LT, abscondbrtarget:$dst)>;
|
||||
def : InstAlias<"bl $dst", (gBCL 20, CR0LT, condbrtarget:$dst)>;
|
||||
def : InstAlias<"bla $dst", (gBCLA 20, CR0LT, abscondbrtarget:$dst)>;
|
||||
def : InstAlias<"blr", (gBCLR 20, CR0LT, 0)>;
|
||||
def : InstAlias<"blrl", (gBCLRL 20, CR0LT, 0)>;
|
||||
def : InstAlias<"bctr", (gBCCTR 20, CR0LT, 0)>;
|
||||
def : InstAlias<"bctrl", (gBCCTRL 20, CR0LT, 0)>;
|
||||
|
||||
multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
|
||||
def : InstAlias<"b"#name#pm#" $cc, $dst",
|
||||
(BCC bibo, crrc:$cc, condbrtarget:$dst)>;
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file defines the SchedModel for the POWER7 processor.
|
||||
// This file defines the itinerary class data for the POWER7 processor.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -116,17 +116,13 @@ let SchedModel = P7Model in {
|
||||
(instregex "^B(L)?(A)?(8)?(_NOP|_NOTOC)?(_TLS|_RM)?(_)?$")>;
|
||||
|
||||
def : InstRW<[P7_BRU_3C, P7_DISP_BR], (instrs
|
||||
BDZLRLp, BDZLRm, BDZLRp, BDZLm, BDZLp, BDZm, BDZp,
|
||||
BDNZ, BDNZ8, BDNZA, BDNZAm, BDNZAp, BDNZL, BDNZLA, BDNZLAm, BDNZLAp, BDNZLR,
|
||||
BDNZLR8, BDNZLRL, BDNZLRLm, BDNZLRLp, BDNZLRm, BDNZLRp, BDNZLm, BDNZLp,
|
||||
BDNZm, BDNZp, BDZ, BDZ8, BDZA, BDZAm, BDZAp, BDZL, BDZLA, BDZLAm, BDZLAp,
|
||||
BDZLR, BDZLR8, BDZLRL, BDZLRLm, BLR, BLR8, BLRL, BCL, BCLR, BCLRL, BCLRLn,
|
||||
BCLRn, BCLalways, BCLn, BCTR, BCTR8, BCTRL, BCTRL8, BCTRL8_LDinto_toc,
|
||||
BLR, BLR8, BLRL, BCL, BCLR, BCLRL,
|
||||
BCTR, BCTR8, BCTRL, BCTRL8, BCTRL8_LDinto_toc,
|
||||
BCTRL8_LDinto_toc_RM, BCTRL8_RM, BCTRL_LWZinto_toc, BCTRL_LWZinto_toc_RM,
|
||||
BCTRL_RM, BCn, BC, BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL,
|
||||
BCCLA, BCCLR, BCCLRL, BCCTR, BCCTR8, BCCTR8n, BCCTRL, BCCTRL8,
|
||||
BCTRL_RM, BC, BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL,
|
||||
BCCLA, BCCLR, BCCLRL, BCCTR, BCCTR8, BCCTRL, BCCTRL8,
|
||||
BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCCLRL, BCCTR,
|
||||
BCCTR8, BCCTR8n, BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, BCCTRn, gBC, gBCA,
|
||||
BCCTR8, BCCTRL, BCCTRL8, gBC, gBCA,
|
||||
gBCAat, gBCCTR, gBCCTRL, gBCL, gBCLA, gBCLAat, gBCLR, gBCLRL, gBCLat, gBCat,
|
||||
MFCTR, MFCTR8, MFLR, MFLR8
|
||||
)>;
|
||||
|
||||
@ -303,7 +303,6 @@ let SchedModel = P8Model in {
|
||||
|
||||
def : InstRW<[P8_BR_2C, P8_ISSUE_BR], (instrs
|
||||
(instregex "^(g)?B(C)?(C)?(CTR)?(L)?(A)?(R)?(L)?(8)?(_LD|_LWZ)?(always|into_toc|at)?(_RM)?(n)?$"),
|
||||
(instregex "^BD(N)?Z(L)?(R|A)?(L)?(m|p|8)?$"),
|
||||
(instregex "^BL(R|A)?(8)?(_NOP)?(_TLS)?(_)?(RM)?$"))>;
|
||||
|
||||
// Instructions of DFP pipeline
|
||||
|
||||
Loading…
Reference in New Issue
Block a user