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[GlobalISel][X86] Remove hand-written G_FADD/F_SUB selection.

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Now it handle by TableGen.

llvm-svn: 302793
This commit is contained in:
Igor Breger 2017-05-11 12:15:03 +00:00
parent f2cd0f9d05
commit a44fc83d9f
1 changed files with 0 additions and 105 deletions
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105
llvm/lib/Target/X86/X86InstructionSelector.cpp
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@ -56,13 +56,9 @@ private:
bool selectImpl(MachineInstr &I) const;
// TODO: remove after suported by Tablegen-erated instruction selection.
unsigned getFAddOp(LLT &Ty, const RegisterBank &RB) const;
unsigned getFSubOp(LLT &Ty, const RegisterBank &RB) const;
unsigned getLoadStoreOp(LLT &Ty, const RegisterBank &RB, unsigned Opc,
uint64_t Alignment) const;
bool selectBinaryOp(MachineInstr &I, MachineRegisterInfo &MRI,
MachineFunction &MF) const;
bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
MachineFunction &MF) const;
bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
@ -235,8 +231,6 @@ bool X86InstructionSelector::select(MachineInstr &I) const {
DEBUG(dbgs() << " C++ instruction selection: "; I.print(dbgs()));
// TODO: This should be implemented by tblgen.
if (selectBinaryOp(I, MRI, MF))
return true;
if (selectLoadStoreOp(I, MRI, MF))
return true;
if (selectFrameIndexOrGep(I, MRI, MF))
@ -253,105 +247,6 @@ bool X86InstructionSelector::select(MachineInstr &I) const {
return false;
}
unsigned X86InstructionSelector::getFAddOp(LLT &Ty,
const RegisterBank &RB) const {
if (X86::VECRRegBankID != RB.getID())
return TargetOpcode::G_FADD;
if (Ty == LLT::scalar(32)) {
if (STI.hasAVX512()) {
return X86::VADDSSZrr;
} else if (STI.hasAVX()) {
return X86::VADDSSrr;
} else if (STI.hasSSE1()) {
return X86::ADDSSrr;
}
} else if (Ty == LLT::scalar(64)) {
if (STI.hasAVX512()) {
return X86::VADDSDZrr;
} else if (STI.hasAVX()) {
return X86::VADDSDrr;
} else if (STI.hasSSE2()) {
return X86::ADDSDrr;
}
} else if (Ty == LLT::vector(4, 32)) {
if ((STI.hasAVX512()) && (STI.hasVLX())) {
return X86::VADDPSZ128rr;
} else if (STI.hasAVX()) {
return X86::VADDPSrr;
} else if (STI.hasSSE1()) {
return X86::ADDPSrr;
}
}
return TargetOpcode::G_FADD;
}
unsigned X86InstructionSelector::getFSubOp(LLT &Ty,
const RegisterBank &RB) const {
if (X86::VECRRegBankID != RB.getID())
return TargetOpcode::G_FSUB;
if (Ty == LLT::scalar(32)) {
if (STI.hasAVX512()) {
return X86::VSUBSSZrr;
} else if (STI.hasAVX()) {
return X86::VSUBSSrr;
} else if (STI.hasSSE1()) {
return X86::SUBSSrr;
}
} else if (Ty == LLT::scalar(64)) {
if (STI.hasAVX512()) {
return X86::VSUBSDZrr;
} else if (STI.hasAVX()) {
return X86::VSUBSDrr;
} else if (STI.hasSSE2()) {
return X86::SUBSDrr;
}
} else if (Ty == LLT::vector(4, 32)) {
if ((STI.hasAVX512()) && (STI.hasVLX())) {
return X86::VSUBPSZ128rr;
} else if (STI.hasAVX()) {
return X86::VSUBPSrr;
} else if (STI.hasSSE1()) {
return X86::SUBPSrr;
}
}
return TargetOpcode::G_FSUB;
}
bool X86InstructionSelector::selectBinaryOp(MachineInstr &I,
MachineRegisterInfo &MRI,
MachineFunction &MF) const {
const unsigned DefReg = I.getOperand(0).getReg();
LLT Ty = MRI.getType(DefReg);
const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
unsigned NewOpc = I.getOpcode();
switch (NewOpc) {
case TargetOpcode::G_FADD:
NewOpc = getFAddOp(Ty, RB);
break;
case TargetOpcode::G_FSUB:
NewOpc = getFSubOp(Ty, RB);
break;
default:
break;
}
if (NewOpc == I.getOpcode())
return false;
I.setDesc(TII.get(NewOpc));
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
}
unsigned X86InstructionSelector::getLoadStoreOp(LLT &Ty, const RegisterBank &RB,
unsigned Opc,
uint64_t Alignment) const {