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[MC][ARM] Fix number of operands of tMOVSr

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Differential revision: https://reviews.llvm.org/D92029
This commit is contained in:
Evgeny Leviant 2020-11-24 18:13:10 +03:00
parent a8de412f51
commit a6a6d11c7b
2 changed files with 12 additions and 3 deletions
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9
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -10309,11 +10309,14 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
!HasWideQualifier) {
// The operands aren't the same for tMOV[S]r... (no cc_out)
MCInst TmpInst;
TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
unsigned Op = Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr;
TmpInst.setOpcode(Op);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(1));
TmpInst.addOperand(Inst.getOperand(2));
TmpInst.addOperand(Inst.getOperand(3));
if (Op == ARM::tMOVr) {
TmpInst.addOperand(Inst.getOperand(2));
TmpInst.addOperand(Inst.getOperand(3));
}
Inst = TmpInst;
return true;
}

6
llvm/test/MC/ARM/tMOVSr.s Normal file
View File

@ -0,0 +1,6 @@
@ REQUIRES: asserts
@ RUN: llvm-mc --triple=thumbv8 --debug %s 2>&1 | FileCheck %s --match-full-lines
@ CHECK: Changed to: <MCInst #{{[0-9]+}} tMOVSr <MCOperand Reg:{{[0-9]+}}> <MCOperand Reg:{{[0-9]+}}>>
.text
movs r2, r3