Magic-Mirror/llvm-capstone
1
0
Fork 0
mirror of https://github.com/capstone-engine/llvm-capstone.git synced 2024-10-09 04:14:11 +00:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

Avoid cppcheck operator precedence warnings. NFCI.

Browse Source 
Prefer ((X & Y) ? A : B) to (X & Y ? A : B)

llvm-svn: 359884
This commit is contained in:
Simon Pilgrim 2019-05-03 13:50:38 +00:00
parent 2c8936fd26
commit aa49be4926
6 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Bitcode/Reader/MetadataLoader.cpp
View File

@ -103,7 +103,7 @@ static cl::opt<bool> DisableLazyLoading(
namespace {
static int64_t unrotateSign(uint64_t U) { return U & 1 ? ~(U >> 1) : U >> 1; }
static int64_t unrotateSign(uint64_t U) { return (U & 1) ? ~(U >> 1) : U >> 1; }
class BitcodeReaderMetadataList {
/// Array of metadata references.

2
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
View File

@ -1613,7 +1613,7 @@ static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
case AArch64::MOVIv4s_msl:
case AArch64::MVNIv2s_msl:
case AArch64::MVNIv4s_msl:
Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108));
Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
break;
}

4
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -10994,10 +10994,10 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
// When the operand is immediate, using the two least significant bits of
// the immediate to set the bits 62:63 of FPSCR.
unsigned Mode = MI.getOperand(1).getImm();
BuildMI(*BB, MI, dl, TII->get(Mode & 1 ? PPC::MTFSB1 : PPC::MTFSB0))
BuildMI(*BB, MI, dl, TII->get((Mode & 1) ? PPC::MTFSB1 : PPC::MTFSB0))
.addImm(31);
BuildMI(*BB, MI, dl, TII->get(Mode & 2 ? PPC::MTFSB1 : PPC::MTFSB0))
BuildMI(*BB, MI, dl, TII->get((Mode & 2) ? PPC::MTFSB1 : PPC::MTFSB0))
.addImm(30);
} else if (MI.getOpcode() == PPC::SETRND) {
DebugLoc dl = MI.getDebugLoc();

2
llvm/lib/Target/X86/Utils/X86ShuffleDecode.cpp
View File

@ -299,7 +299,7 @@ void DecodeVPERM2X128Mask(unsigned NumElts, unsigned Imm,
unsigned HalfMask = Imm >> (l * 4);
unsigned HalfBegin = (HalfMask & 0x3) * HalfSize;
for (unsigned i = HalfBegin, e = HalfBegin + HalfSize; i != e; ++i)
ShuffleMask.push_back(HalfMask & 8 ? SM_SentinelZero : (int)i);
ShuffleMask.push_back((HalfMask & 8) ? SM_SentinelZero : (int)i);
}
}

2
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -11577,7 +11577,7 @@ static SDValue lowerShuffleAsSpecificZeroOrAnyExtend(
DAG.getBitcast(MVT::v4i32, InputV),
getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
int PSHUFWMask[4] = {1, -1, -1, -1};
unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
unsigned OddEvenOp = (Offset & 1) ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
return DAG.getBitcast(
VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
DAG.getBitcast(MVT::v8i16, InputV),

2
llvm/tools/llvm-stress/llvm-stress.cpp
View File

@ -276,7 +276,7 @@ protected:
/// Pick a random type.
Type *pickType() {
return (getRandom() & 1 ? pickVectorType() : pickScalarType());
return (getRandom() & 1) ? pickVectorType() : pickScalarType();
}
/// Pick a random pointer type.