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[Simplify] Use execution order of memory accesses.

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Iterate through memory accesses in execution order (first all implicit reads,
then explicit accesses, then implicit writes).

In the test case this caused an implicit load to be handled as if it was loaded
after the write. That is, the value being written before it is available.

This fixes llvm.org/PR33323

llvm-svn: 304810
This commit is contained in:
Michael Kruse 2017-06-06 17:46:42 +00:00
parent 2f1556726c
commit ad7a1805be
4 changed files with 128 additions and 1 deletions
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3
polly/lib/Transform/Simplify.cpp
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@ -134,7 +134,8 @@ private:
auto TargetsSpace = Targets.get_space();
bool Started = Stmt->isRegionStmt();
for (auto *Acc : *Stmt) {
auto Accesses = getAccessesInOrder(*Stmt);
for (auto *Acc : Accesses) {
if (Acc->isLatestScalarKind())
continue;

48
polly/test/Simplify/pr33323.ll Normal file
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@ -0,0 +1,48 @@
; RUN: opt %loadPolly -polly-import-jscop -polly-import-jscop-dir=%S -polly-import-jscop-postfix=transformed -polly-simplify -analyze < %s | FileCheck %s
;
; llvm.org/PR33323
;
; Do not remove the pair (store double %add119, read %add119) as redundant
; because the are in the wrong order.
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
define fastcc void @pr33323([1000 x double]* nocapture %data, [1000 x double]* nocapture %symmat) {
entry:
br label %for.body98
for.cond87.loopexit:
ret void
for.body98:
%indvars.iv13 = phi i64 [ 1, %entry ], [ %indvars.iv.next14, %for.end122 ]
br label %for.body105
for.body105:
%indvars.iv = phi i64 [ 0, %for.body98 ], [ %indvars.iv.next, %for.body105 ]
%arrayidx109 = getelementptr inbounds [1000 x double], [1000 x double]* %data, i64 %indvars.iv, i64 0
%add119 = fadd double undef, undef
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%exitcond = icmp eq i64 %indvars.iv.next, 1000
br i1 %exitcond, label %for.end122, label %for.body105
for.end122:
%arrayidx130 = getelementptr inbounds [1000 x double], [1000 x double]* %symmat, i64 %indvars.iv13, i64 0
store double %add119, double* %arrayidx130
%indvars.iv.next14 = add nuw nsw i64 %indvars.iv13, 1
%exitcond15 = icmp eq i64 %indvars.iv.next14, 1000
br i1 %exitcond15, label %for.cond87.loopexit, label %for.body98
}
; CHECK: Statistics {
; CHECK: Redundant writes removed: 1
; CHECK: Stmts removed: 1
; CHECK: }
; CHECK: After accesses {
; CHECK-NEXT: Stmt_for_body105
; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 1]
; CHECK-NEXT: { Stmt_for_body105[i0, i1] -> MemRef_add119[] };
; CHECK-NEXT: new: { Stmt_for_body105[i0, i1] -> MemRef_symmat[1 + i0, 0] };
; CHECK-NEXT: }

39
polly/test/Simplify/pr33323___%for.body98---%for.cond87.loopexit.jscop Normal file
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@ -0,0 +1,39 @@
{
"arrays" : [
{
"name" : "MemRef_symmat",
"sizes" : [ "*", "1000" ],
"type" : "double"
}
],
"context" : "{ : }",
"name" : "%for.body98---%for.cond87.loopexit",
"statements" : [
{
"accesses" : [
{
"kind" : "write",
"relation" : "{ Stmt_for_body105[i0, i1] -> MemRef_add119[] }"
}
],
"domain" : "{ Stmt_for_body105[i0, i1] : 0 <= i0 <= 998 and 0 <= i1 <= 999 }",
"name" : "Stmt_for_body105",
"schedule" : "{ Stmt_for_body105[i0, i1] -> [i0, 0, i1] }"
},
{
"accesses" : [
{
"kind" : "write",
"relation" : "{ Stmt_for_end122[i0] -> MemRef_symmat[1 + i0, 0] }"
},
{
"kind" : "read",
"relation" : "{ Stmt_for_end122[i0] -> MemRef_add119[] }"
}
],
"domain" : "{ Stmt_for_end122[i0] : 0 <= i0 <= 998 }",
"name" : "Stmt_for_end122",
"schedule" : "{ Stmt_for_end122[i0] -> [i0, 1, 0] }"
}
]
}

39
polly/test/Simplify/pr33323___%for.body98---%for.cond87.loopexit.jscop.transformed Normal file
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@ -0,0 +1,39 @@
{
"arrays" : [
{
"name" : "MemRef_symmat",
"sizes" : [ "*", "1000" ],
"type" : "double"
}
],
"context" : "{ : }",
"name" : "%for.body98---%for.cond87.loopexit",
"statements" : [
{
"accesses" : [
{
"kind" : "write",
"relation" : "{ Stmt_for_body105[i0, i1] -> MemRef_symmat[1 + i0, 0] }"
}
],
"domain" : "{ Stmt_for_body105[i0, i1] : 0 <= i0 <= 998 and 0 <= i1 <= 999 }",
"name" : "Stmt_for_body105",
"schedule" : "{ Stmt_for_body105[i0, i1] -> [i0, 0, i1] }"
},
{
"accesses" : [
{
"kind" : "write",
"relation" : "{ Stmt_for_end122[i0] -> MemRef_symmat[1 + i0, 0] }"
},
{
"kind" : "read",
"relation" : "{ Stmt_for_end122[i0] -> MemRef_symmat[1 + i0, 0] }"
}
],
"domain" : "{ Stmt_for_end122[i0] : 0 <= i0 <= 998 }",
"name" : "Stmt_for_end122",
"schedule" : "{ Stmt_for_end122[i0] -> [i0, 1, 0] }"
}
]
}