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[PowerPC] PPC backend optimization on conditional trap intrustions
This patch adds PPC back end optimization to analyze the arguments of a conditional trap instruction to execute one of the following: 1. Delete it if never trap 2. Replace it if always trap 3. Otherwise keep it Reviewed By: nemanjai, amyk, PowerPC Differential revision: https://reviews.llvm.org/D111434
This commit is contained in:
Victor Huang
parent
877d6e9b9a
commit
ae27ca9a67
@ -378,6 +378,7 @@ static void convertUnprimedAccPHIs(const PPCInstrInfo *TII,
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// Perform peephole optimizations.
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bool PPCMIPeephole::simplifyCode(void) {
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bool Simplified = false;
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bool TrapOpt = false;
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MachineInstr* ToErase = nullptr;
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std::map<MachineInstr *, bool> TOCSaves;
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const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
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@ -419,6 +420,13 @@ bool PPCMIPeephole::simplifyCode(void) {
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ToErase->eraseFromParent();
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ToErase = nullptr;
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}
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// If a conditional trap instruction got optimized to an
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// unconditional trap, eliminate all the instructions between
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// the trap and the terminator of the MBB.
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if (TrapOpt && !MI.isTerminator()) {
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ToErase = &MI;
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continue;
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}
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// Ignore debug instructions.
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if (MI.isDebugInstr())
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@ -1006,6 +1014,50 @@ bool PPCMIPeephole::simplifyCode(void) {
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++NumRotatesCollapsed;
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break;
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}
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// We will replace TD/TW/TDI/TWI with an unconditional trap if it will
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// always trap, we will delete the node if it will never trap.
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case PPC::TDI:
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case PPC::TWI:
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case PPC::TD:
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case PPC::TW: {
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MachineInstr *LiMI1 = getVRegDefOrNull(&MI.getOperand(1), MRI);
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MachineInstr *LiMI2 = getVRegDefOrNull(&MI.getOperand(2), MRI);
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unsigned Opcode1 = LiMI1->getOpcode();
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unsigned Opcode2 = LiMI2->getOpcode();
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bool IsOperand2Immediate = MI.getOperand(2).isImm();
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// We can only do the optimization if we can get immediates
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// from both operands
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if (!(LiMI1 && (Opcode1 == PPC::LI || Opcode1 == PPC::LI8)))
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break;
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if (!IsOperand2Immediate &&
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!(LiMI2 && (Opcode2 == PPC::LI || Opcode2 == PPC::LI8)))
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break;
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auto ImmOperand0 = MI.getOperand(0).getImm();
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auto ImmOperand1 = LiMI1->getOperand(1).getImm();
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auto ImmOperand2 = IsOperand2Immediate ? MI.getOperand(2).getImm()
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: LiMI2->getOperand(1).getImm();
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// We will replace the MI with an unconditional trap if it will always
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// trap.
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if ((ImmOperand0 == 31) ||
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((ImmOperand0 & 0x10) &&
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((int64_t)ImmOperand1 < (int64_t)ImmOperand2)) ||
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((ImmOperand0 & 0x8) &&
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((int64_t)ImmOperand1 > (int64_t)ImmOperand2)) ||
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((ImmOperand0 & 0x2) &&
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((uint64_t)ImmOperand1 < (uint64_t)ImmOperand2)) ||
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((ImmOperand0 & 0x1) &&
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((uint64_t)ImmOperand1 > (uint64_t)ImmOperand2)) ||
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((ImmOperand0 & 0x4) && (ImmOperand1 == ImmOperand2))) {
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BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::TRAP));
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TrapOpt = true;
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}
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// We will delete the MI if it will never trap.
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ToErase = &MI;
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Simplified = true;
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break;
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}
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}
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}
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@ -1015,6 +1067,8 @@ bool PPCMIPeephole::simplifyCode(void) {
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ToErase->eraseFromParent();
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ToErase = nullptr;
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}
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// Reset TrapOpt to false at the end of the basic block.
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TrapOpt = false;
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}
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// Eliminate all the TOC save instructions which are redundant.
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747
llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir
Normal file
747
llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir
Normal file
@ -0,0 +1,747 @@
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# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \
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# RUN: -verify-machineinstrs -start-before=ppc-mi-peepholes | FileCheck %s
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---
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name: conditional_trap_opt_reg_implicit_def
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = IMPLICIT_DEF
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%1:gprc = IMPLICIT_DEF
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%2:g8rc = IMPLICIT_DEF
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%3:g8rc = IMPLICIT_DEF
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TW 8, %0, %1
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TD 8, %2, %3
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TWI 24, %0, 0
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TDI 24, %2, 0
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_reg_implicit_def
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: twgt 3, 3
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# CHECK-NEXT: tdgt 3, 3
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# CHECK-NEXT: twnei 3, 0
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# CHECK-NEXT: tdnei 3, 0
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TW_31
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI 3
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%1:gprc = LI 0
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TW 31, %1, %0
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TW_31
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: trap
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TW_24
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI 3
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%1:gprc = LI 0
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TW 24, %1, %0
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TW_24
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: trap
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_no_trap_TW_24
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI 3
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%1:gprc = LI 3
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TW 24, %1, %0
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_no_trap_TW_24
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TW_20
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI 3
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%1:gprc = LI 3
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TW 20, %1, %0
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TW_20
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: trap
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_no_trap_TW_20
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI 3
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%1:gprc = LI 5
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TW 20, %1, %0
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_no_trap_TW_20
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_no_trap_TW_16
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI 5
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%1:gprc = LI 1
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TW 16, %0, %1
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_no_trap_TW_16
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TW_16
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI 5
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%1:gprc = LI 1
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TW 16, %1, %0
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TW 16, %0, %1
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TW_16
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: trap
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TW_8
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI -1
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%1:gprc = LI 10
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TW 8, %1, %0
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TW 8, %0, %1
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TW_8
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: trap
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TW_2
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI -1
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%1:gprc = LI 2
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TW 2, %1, %0
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TW 2, %0, %1
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TW_2
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: trap
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TW_1
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI -3
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%1:gprc = LI 4
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TW 1, %1, %0
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TW 1, %0, %1
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TW_1
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: trap
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TW_4
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI 5
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%1:gprc = LI 1
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TW 4, %1, %0
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TW 4, %1, %1
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TW_4
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: trap
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TWI_31
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI 3
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TWI 31, %0, 0
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TWI_31
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: trap
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TWI_24
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI 3
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TWI 24, %0, 0
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TWI_24
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: trap
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_no_trap_TWI_24
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI 0
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TWI 24, %0, 0
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_no_trap_TWI_24
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TWI_20
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI 3
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TWI 20, %0, 3
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TWI_20
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: trap
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_no_trap_TWI_20
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI 3
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TWI 20, %0, 0
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_no_trap_TWI_20
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_no_trap_TWI_16
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI 5
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TWI 16, %0, 1
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_no_trap_TWI_16
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TWI_16
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI 5
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%1:gprc = LI 1
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TWI 16, %1, 5
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TWI 16, %0, 1
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TWI_16
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: trap
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TWI_8
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI -1
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%1:gprc = LI 10
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TWI 8, %1, -1
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TWI 8, %0, 10
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TWI_8
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: trap
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TWI_2
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI -1
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%1:gprc = LI 2
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TWI 2, %1, -1
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TWI 2, %0, 2
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TWI_2
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: trap
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TWI_1
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI -3
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%1:gprc = LI 4
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TWI 1, %1, -3
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TWI 1, %0, 4
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TWI_1
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: trap
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TWI_4
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:gprc = LI 5
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%1:gprc = LI 1
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TWI 4, %1, 5
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TWI 4, %1, 1
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TWI_4
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# CHECK: # %bb.0: # %entry
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# CHECK-NEXT: trap
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# CHECK-NEXT: blr
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---
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name: conditional_trap_opt_TD_31
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alignment: 16
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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%0:g8rc = LI8 3
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%1:g8rc = LI8 0
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TD 31, %1, %0
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BLR8 implicit $lr8, implicit $rm
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...
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# CHECK-LABEL: conditional_trap_opt_TD_31
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_TD_24
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 3
|
||||
%1:g8rc = LI8 0
|
||||
TD 24, %1, %0
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_TD_24
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_no_trap_TD_24
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 3
|
||||
%1:g8rc = LI8 3
|
||||
TD 24, %1, %0
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_no_trap_TD_24
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_TD_20
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 3
|
||||
%1:g8rc = LI8 3
|
||||
TD 20, %1, %0
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_TD_20
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_no_trap_TD_20
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 3
|
||||
%1:g8rc = LI8 5
|
||||
TD 20, %1, %0
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_no_trap_TD_20
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_no_trap_TD_16
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 5
|
||||
%1:g8rc = LI8 1
|
||||
TD 16, %0, %1
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_no_trap_TD_16
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_TD_16
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 5
|
||||
%1:g8rc = LI8 1
|
||||
TD 16, %1, %0
|
||||
TD 16, %0, %1
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_TD_16
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_TD_8
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 -1
|
||||
%1:g8rc = LI8 10
|
||||
TD 8, %1, %0
|
||||
TD 8, %0, %1
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_TD_8
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_TD_2
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 -1
|
||||
%1:g8rc = LI8 2
|
||||
TD 2, %1, %0
|
||||
TD 2, %0, %1
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_TD_2
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_TD_1
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 -3
|
||||
%1:g8rc = LI8 4
|
||||
TD 1, %1, %0
|
||||
TD 1, %0, %1
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_TD_1
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_TD_4
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 5
|
||||
%1:g8rc = LI8 1
|
||||
TD 4, %1, %0
|
||||
TD 4, %1, %1
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_TD_4
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_TDI_31
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 3
|
||||
TDI 31, %0, 0
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_TDI_31
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_TDI_24
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 3
|
||||
TDI 24, %0, 0
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_TDI_24
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_no_trap_TDI_24
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 0
|
||||
TDI 24, %0, 0
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_no_trap_TDI_24
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_TDI_20
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 3
|
||||
TDI 20, %0, 3
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_TDI_20
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_no_trap_TDI_20
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 5
|
||||
TDI 20, %0, 3
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_no_trap_TDI_20
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_no_trap_TDI_16
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 5
|
||||
TDI 16, %0, 1
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_no_trap_TDI_16
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_TDI_16
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 5
|
||||
%1:g8rc = LI8 1
|
||||
TDI 16, %1, 5
|
||||
TDI 16, %0, 1
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_TDI_16
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_TDI_8
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 -1
|
||||
%1:g8rc = LI8 10
|
||||
TDI 8, %1, -1
|
||||
TDI 8, %0, 10
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_TDI_8
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_TDI_2
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 -1
|
||||
%1:g8rc = LI8 2
|
||||
TDI 2, %1, -1
|
||||
TDI 2, %0, 2
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_TDI_2
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_TDI_1
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 -3
|
||||
%1:g8rc = LI8 4
|
||||
TDI 1, %1, -3
|
||||
TDI 1, %0, 4
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_TDI_1
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_TDI_4
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:g8rc = LI8 5
|
||||
%1:g8rc = LI8 1
|
||||
TDI 4, %1, 5
|
||||
TDI 4, %1, 1
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_TDI_4
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
|
||||
---
|
||||
name: conditional_trap_opt_multiple_traps
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
%0:gprc = LI 5
|
||||
%1:gprc = LI 1
|
||||
%2:g8rc = LI8 -1
|
||||
%3:g8rc = LI8 0
|
||||
TWI 31, %1, 5
|
||||
TDI 31, %3, 0
|
||||
TW 31, %0, %1
|
||||
TD 31, %2, %2
|
||||
BLR8 implicit $lr8, implicit $rm
|
||||
...
|
||||
# CHECK-LABEL: conditional_trap_opt_multiple_traps
|
||||
# CHECK: # %bb.0: # %entry
|
||||
# CHECK-NEXT: trap
|
||||
# CHECK-NEXT: blr
|
||||
Loading…
Reference in New Issue
Block a user