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[AArch64] add tests for bitcasted DUPLANE; NFC
See D63815 for context/motivation.
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@ -1660,6 +1660,46 @@ entry:
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ret <2 x float> %mul
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}
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define <2 x float> @test_vmul_laneq3_f32_bitcast(<2 x float> %a, <2 x double> %v) {
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; CHECK-LABEL: test_vmul_laneq3_f32_bitcast:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
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; CHECK-NEXT: fmul v0.2s, v0.2s, v1.s[1]
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; CHECK-NEXT: ret
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%extract = shufflevector <2 x double> %v, <2 x double> undef, <1 x i32> <i32 1>
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%bc = bitcast <1 x double> %extract to <2 x float>
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%splat = shufflevector <2 x float> %bc, <2 x float> undef, <2 x i32> <i32 1, i32 1>
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%mul = fmul <2 x float> %splat, %a
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ret <2 x float> %mul
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}
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define <2 x float> @test_vmul_laneq2_f32_bitcast(<2 x float> %a, <2 x double> %v) {
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; CHECK-LABEL: test_vmul_laneq2_f32_bitcast:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
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; CHECK-NEXT: fmul v0.2s, v0.2s, v1.s[0]
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; CHECK-NEXT: ret
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%extract = shufflevector <2 x double> %v, <2 x double> undef, <1 x i32> <i32 1>
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%bc = bitcast <1 x double> %extract to <2 x float>
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%splat = shufflevector <2 x float> %bc, <2 x float> undef, <2 x i32> <i32 0, i32 0>
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%mul = fmul <2 x float> %splat, %a
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ret <2 x float> %mul
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}
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define <4 x i16> @test_vmul_laneq5_i16_bitcast(<4 x i16> %a, <2 x double> %v) {
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; CHECK-LABEL: test_vmul_laneq5_i16_bitcast:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
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; CHECK-NEXT: dup v1.4h, v1.h[1]
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; CHECK-NEXT: add v0.4h, v1.4h, v0.4h
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; CHECK-NEXT: ret
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%extract = shufflevector <2 x double> %v, <2 x double> undef, <1 x i32> <i32 1>
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%bc = bitcast <1 x double> %extract to <4 x i16>
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%splat = shufflevector <4 x i16> %bc, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%r = add <4 x i16> %splat, %a
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ret <4 x i16> %r
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}
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define <1 x double> @test_vmul_laneq_f64(<1 x double> %a, <2 x double> %v) {
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; CHECK-LABEL: test_vmul_laneq_f64:
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; CHECK: // %bb.0: // %entry
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