GlobalISel: translate insertvalue instructions.

This adds a G_INSERT instruction, which technically makes G_SEQUENCE redundant
(it's equivalent to a G_INSERT into an IMPLICIT_DEF). We'll leave G_SEQUENCE
for now though: it's likely to be far more common as it's a fundamental part of
legalization, so avoiding the mess and bloat of the extra IMPLICIT_DEFs is
probably worthwhile.

llvm-svn: 279306

llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h

@@ -151,6 +151,8 @@ private:
 
   bool translateExtractValue(const User &U);
 
+  bool translateInsertValue(const User &U);
+
   /// Translate return (ret) instruction.
   /// The target needs to implement CallLowering::lowerReturn for
   /// this to succeed.
@@ -268,7 +270,6 @@ private:
   bool translateExtractElement(const User &U) { return false; }
   bool translateInsertElement(const User &U) { return false; }
   bool translateShuffleVector(const User &U) { return false; }
-  bool translateInsertValue(const User &U) { return false; }
   bool translateLandingPad(const User &U) { return false; }
 
   /// @}

llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

@@ -269,6 +269,15 @@ public:
     return MIB;
   }
 
+  template <typename... ArgTys>
+  MachineInstrBuilder buildInsert(LLT Ty, unsigned Res, unsigned Src, LLT OpTy,
+                                  unsigned Op, unsigned Index, ArgTys... Args) {
+    MachineInstrBuilder MIB =
+        buildInstr(TargetOpcode::G_INSERT, Ty).addDef(Res).addUse(Src);
+    addUsesWithIndices(MIB, OpTy, Op, Index, Args...);
+    return MIB;
+  }
+
   /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
   /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
   /// result register definition unless \p Reg is NoReg (== 0). The second

llvm/include/llvm/Target/GenericOpcodes.td

@@ -317,6 +317,15 @@ def G_EXTRACT : Instruction {
 
 // Combine a sequence of generic vregs into a single larger value (starting at
 // bit 0).
+def G_INSERT : Instruction {
+  let OutOperandList = (outs unknown:$dst);
+  let InOperandList = (ins unknown:$src, variable_ops);
+  let hasSideEffects = 0;
+}
+
+// Combine a sequence of generic vregs into a single larger value (starting at
+// bit 0). Essentially a G_INSERT where $src is an IMPLICIT_DEF, but it's so
+// important to legalization it probably deserves its own instruction.
 def G_SEQUENCE : Instruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins variable_ops);

llvm/include/llvm/Target/TargetOpcodes.def

@@ -199,6 +199,10 @@ HANDLE_TARGET_OPCODE(G_FRAME_INDEX)
 /// (typically a sub-register COPY after instruction selection).
 HANDLE_TARGET_OPCODE(G_EXTRACT)
 
+/// Generic instruction to insert blocks of bits from the registers given into
+/// the source.
+HANDLE_TARGET_OPCODE(G_INSERT)
+
 /// Generic instruction to paste a variable number of components together into a
 /// larger register.
 HANDLE_TARGET_OPCODE(G_SEQUENCE)

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

@@ -203,6 +203,30 @@ bool IRTranslator::translateExtractValue(const User &U) {
   return true;
 }
 
+bool IRTranslator::translateInsertValue(const User &U) {
+  const InsertValueInst &IVI = cast<InsertValueInst>(U);
+  const Value *Src = IVI.getAggregateOperand();
+  Type *Int32Ty = Type::getInt32Ty(IVI.getContext());
+  SmallVector<Value *, 1> Indices;
+
+  // getIndexedOffsetInType is designed for GEPs, so the first index is the
+  // usual array element rather than looking into the actual aggregate.
+  Indices.push_back(ConstantInt::get(Int32Ty, 0));
+  for (auto Idx : IVI.indices())
+    Indices.push_back(ConstantInt::get(Int32Ty, Idx));
+
+  uint64_t Offset = 8 * DL->getIndexedOffsetInType(Src->getType(), Indices);
+
+  unsigned Res = getOrCreateVReg(IVI);
+  const Value &Inserted = *IVI.getInsertedValueOperand();
+  MIRBuilder.buildInsert(
+      LLT{*IVI.getType(), DL}, Res, getOrCreateVReg(*IVI.getAggregateOperand()),
+      LLT{*Inserted.getType(), DL}, getOrCreateVReg(Inserted), Offset);
+
+  return true;
+}
+
+
 bool IRTranslator::translateBitCast(const User &U) {
   if (LLT{*U.getOperand(0)->getType()} == LLT{*U.getType()}) {
     unsigned &Reg = ValToVReg[&U];

llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

@@ -704,3 +704,28 @@ define void @test_extractvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
   store {i8, i32} %res, {i8, i32}* %addr2
   ret void
 }
+
+; CHECK-LABEL: name: test_insertvalue
+; CHECK: [[VAL:%[0-9]+]](32) = COPY %w1
+; CHECK: [[STRUCT:%[0-9]+]](128) = G_LOAD { s128, p0 }
+; CHECK: [[NEWSTRUCT:%[0-9]+]](128) = G_INSERT { s128, s32 } [[STRUCT]], [[VAL]], 64
+; CHECK: G_STORE { s128, p0 } [[NEWSTRUCT]],
+define void @test_insertvalue(%struct.nested* %addr, i32 %val) {
+  %struct = load %struct.nested, %struct.nested* %addr
+  %newstruct = insertvalue %struct.nested %struct, i32 %val, 1, 1
+  store %struct.nested %newstruct, %struct.nested* %addr
+  ret void
+}
+
+; CHECK-LABEL: name: test_insertvalue_agg
+; CHECK: [[SMALLSTRUCT:%[0-9]+]](64) = G_LOAD { s64, p0 }
+; CHECK: [[STRUCT:%[0-9]+]](128) = G_LOAD { s128, p0 }
+; CHECK: [[RES:%[0-9]+]](128) = G_INSERT { s128, s64 } [[STRUCT]], [[SMALLSTRUCT]], 32
+; CHECK: G_STORE { s128, p0 } [[RES]]
+define void @test_insertvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) {
+  %smallstruct = load {i8, i32}, {i8, i32}* %addr2
+  %struct = load %struct.nested, %struct.nested* %addr
+  %res = insertvalue %struct.nested %struct, {i8, i32} %smallstruct, 1
+  store %struct.nested %res, %struct.nested* %addr
+  ret void
+}