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https://github.com/capstone-engine/llvm-capstone.git
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Partially revert r324124 [X86] Add tests for missed opportunities to use ptest for all ones comparison.
Turns out I misunderstood the flag behavior of PTEST because I read the documentation for KORTEST which is different than PTEST/KTEST and made a bad assumption. Keep the test rename though cause that's useful. llvm-svn: 324129
This commit is contained in:
Craig Topper
parent
88df555d05
commit
bd2f6e9570
@ -240,272 +240,3 @@ define i32 @vecsel512(<16 x i32> %input, i32 %a, i32 %b) {
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%t2 = select i1 %t1, i32 %a, i32 %b
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ret i32 %t2
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}
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define i32 @veccond128_ones(<4 x i32> %input) {
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; SSE41-LABEL: veccond128_ones:
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; SSE41: # %bb.0: # %entry
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; SSE41-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE41-NEXT: pcmpeqb %xmm0, %xmm1
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; SSE41-NEXT: pmovmskb %xmm1, %eax
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; SSE41-NEXT: cmpl $65535, %eax # imm = 0xFFFF
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; SSE41-NEXT: je .LBB9_2
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; SSE41-NEXT: # %bb.1: # %if-true-block
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; SSE41-NEXT: xorl %eax, %eax
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; SSE41-NEXT: retq
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; SSE41-NEXT: .LBB9_2: # %endif-block
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; SSE41-NEXT: movl $1, %eax
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: veccond128_ones:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpmovmskb %xmm0, %eax
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; AVX-NEXT: cmpl $65535, %eax # imm = 0xFFFF
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; AVX-NEXT: je .LBB9_2
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; AVX-NEXT: # %bb.1: # %if-true-block
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; AVX-NEXT: xorl %eax, %eax
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; AVX-NEXT: retq
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; AVX-NEXT: .LBB9_2: # %endif-block
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; AVX-NEXT: movl $1, %eax
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; AVX-NEXT: retq
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entry:
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%0 = bitcast <4 x i32> %input to i128
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%1 = icmp ne i128 %0, -1
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br i1 %1, label %if-true-block, label %endif-block
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if-true-block:
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ret i32 0
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endif-block:
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ret i32 1
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}
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define i32 @veccond256_ones(<8 x i32> %input) {
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; SSE41-LABEL: veccond256_ones:
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; SSE41: # %bb.0: # %entry
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; SSE41-NEXT: movq %xmm1, %rax
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; SSE41-NEXT: movq %xmm0, %rcx
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; SSE41-NEXT: pextrq $1, %xmm1, %rdx
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; SSE41-NEXT: pextrq $1, %xmm0, %rsi
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; SSE41-NEXT: andq %rdx, %rsi
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; SSE41-NEXT: andq %rax, %rsi
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; SSE41-NEXT: andq %rcx, %rsi
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; SSE41-NEXT: cmpq $-1, %rsi
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; SSE41-NEXT: je .LBB10_2
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; SSE41-NEXT: # %bb.1: # %if-true-block
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; SSE41-NEXT: xorl %eax, %eax
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; SSE41-NEXT: retq
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; SSE41-NEXT: .LBB10_2: # %endif-block
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; SSE41-NEXT: movl $1, %eax
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: veccond256_ones:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX-NEXT: vmovq %xmm1, %rax
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; AVX-NEXT: vmovq %xmm0, %rcx
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; AVX-NEXT: vpextrq $1, %xmm1, %rdx
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; AVX-NEXT: vpextrq $1, %xmm0, %rsi
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; AVX-NEXT: andq %rdx, %rsi
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; AVX-NEXT: andq %rax, %rsi
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; AVX-NEXT: andq %rcx, %rsi
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; AVX-NEXT: cmpq $-1, %rsi
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; AVX-NEXT: je .LBB10_2
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; AVX-NEXT: # %bb.1: # %if-true-block
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; AVX-NEXT: xorl %eax, %eax
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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; AVX-NEXT: .LBB10_2: # %endif-block
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; AVX-NEXT: movl $1, %eax
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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entry:
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%0 = bitcast <8 x i32> %input to i256
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%1 = icmp ne i256 %0, -1
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br i1 %1, label %if-true-block, label %endif-block
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if-true-block:
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ret i32 0
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endif-block:
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ret i32 1
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}
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define i32 @veccond512_ones(<16 x i32> %input) {
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; SSE41-LABEL: veccond512_ones:
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; SSE41: # %bb.0: # %entry
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; SSE41-NEXT: movq %xmm2, %rax
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; SSE41-NEXT: movq %xmm0, %r8
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; SSE41-NEXT: movq %xmm3, %rdx
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; SSE41-NEXT: movq %xmm1, %rsi
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; SSE41-NEXT: andq %rdx, %rsi
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; SSE41-NEXT: andq %rax, %rsi
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; SSE41-NEXT: pextrq $1, %xmm2, %rax
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; SSE41-NEXT: pextrq $1, %xmm0, %rdx
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; SSE41-NEXT: pextrq $1, %xmm3, %rdi
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; SSE41-NEXT: pextrq $1, %xmm1, %rcx
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; SSE41-NEXT: andq %rdi, %rcx
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; SSE41-NEXT: andq %rax, %rcx
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; SSE41-NEXT: andq %rdx, %rcx
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; SSE41-NEXT: andq %rsi, %rcx
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; SSE41-NEXT: andq %r8, %rcx
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; SSE41-NEXT: cmpq $-1, %rcx
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; SSE41-NEXT: je .LBB11_2
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; SSE41-NEXT: # %bb.1: # %if-true-block
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; SSE41-NEXT: xorl %eax, %eax
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; SSE41-NEXT: retq
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; SSE41-NEXT: .LBB11_2: # %endif-block
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; SSE41-NEXT: movl $1, %eax
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: veccond512_ones:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vmovq %xmm1, %rax
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; AVX-NEXT: vmovq %xmm0, %r8
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; AVX-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX-NEXT: vmovq %xmm2, %rdx
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm3
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; AVX-NEXT: vmovq %xmm3, %rsi
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; AVX-NEXT: andq %rdx, %rsi
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; AVX-NEXT: andq %rax, %rsi
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; AVX-NEXT: vpextrq $1, %xmm1, %rax
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; AVX-NEXT: vpextrq $1, %xmm0, %rdx
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; AVX-NEXT: vpextrq $1, %xmm2, %rdi
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; AVX-NEXT: vpextrq $1, %xmm3, %rcx
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; AVX-NEXT: andq %rdi, %rcx
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; AVX-NEXT: andq %rax, %rcx
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; AVX-NEXT: andq %rdx, %rcx
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; AVX-NEXT: andq %rsi, %rcx
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; AVX-NEXT: andq %r8, %rcx
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; AVX-NEXT: cmpq $-1, %rcx
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; AVX-NEXT: je .LBB11_2
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; AVX-NEXT: # %bb.1: # %if-true-block
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; AVX-NEXT: xorl %eax, %eax
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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; AVX-NEXT: .LBB11_2: # %endif-block
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; AVX-NEXT: movl $1, %eax
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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entry:
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%0 = bitcast <16 x i32> %input to i512
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%1 = icmp ne i512 %0, -1
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br i1 %1, label %if-true-block, label %endif-block
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if-true-block:
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ret i32 0
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endif-block:
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ret i32 1
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}
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define i32 @vecsel128_ones(<4 x i32> %input, i32 %a, i32 %b) {
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; SSE41-LABEL: vecsel128_ones:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE41-NEXT: pcmpeqb %xmm0, %xmm1
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; SSE41-NEXT: pmovmskb %xmm1, %eax
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; SSE41-NEXT: cmpl $65535, %eax # imm = 0xFFFF
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; SSE41-NEXT: cmovel %esi, %edi
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; SSE41-NEXT: movl %edi, %eax
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: vecsel128_ones:
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; AVX: # %bb.0:
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpmovmskb %xmm0, %eax
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; AVX-NEXT: cmpl $65535, %eax # imm = 0xFFFF
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; AVX-NEXT: cmovel %esi, %edi
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; AVX-NEXT: movl %edi, %eax
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; AVX-NEXT: retq
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%t0 = bitcast <4 x i32> %input to i128
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%t1 = icmp ne i128 %t0, -1
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%t2 = select i1 %t1, i32 %a, i32 %b
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ret i32 %t2
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}
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define i32 @vecsel256_ones(<8 x i32> %input, i32 %a, i32 %b) {
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; SSE41-LABEL: vecsel256_ones:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movq %xmm1, %rax
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; SSE41-NEXT: movq %xmm0, %r8
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; SSE41-NEXT: pextrq $1, %xmm1, %rdx
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; SSE41-NEXT: pextrq $1, %xmm0, %rcx
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; SSE41-NEXT: andq %rdx, %rcx
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; SSE41-NEXT: andq %rax, %rcx
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; SSE41-NEXT: andq %r8, %rcx
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; SSE41-NEXT: cmpq $-1, %rcx
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; SSE41-NEXT: cmovel %esi, %edi
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; SSE41-NEXT: movl %edi, %eax
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: vecsel256_ones:
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; AVX: # %bb.0:
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX-NEXT: vmovq %xmm1, %r8
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; AVX-NEXT: vmovq %xmm0, %rcx
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; AVX-NEXT: vpextrq $1, %xmm1, %rdx
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; AVX-NEXT: vpextrq $1, %xmm0, %rax
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; AVX-NEXT: andq %rdx, %rax
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; AVX-NEXT: andq %r8, %rax
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; AVX-NEXT: andq %rcx, %rax
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; AVX-NEXT: cmpq $-1, %rax
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; AVX-NEXT: cmovel %esi, %edi
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; AVX-NEXT: movl %edi, %eax
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%t0 = bitcast <8 x i32> %input to i256
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%t1 = icmp ne i256 %t0, -1
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%t2 = select i1 %t1, i32 %a, i32 %b
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ret i32 %t2
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}
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define i32 @vecsel512_ones(<16 x i32> %input, i32 %a, i32 %b) {
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; SSE41-LABEL: vecsel512_ones:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movq %xmm2, %rax
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; SSE41-NEXT: movq %xmm0, %r8
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; SSE41-NEXT: movq %xmm3, %rdx
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; SSE41-NEXT: movq %xmm1, %rcx
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; SSE41-NEXT: andq %rdx, %rcx
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; SSE41-NEXT: andq %rax, %rcx
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; SSE41-NEXT: pextrq $1, %xmm2, %r10
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; SSE41-NEXT: pextrq $1, %xmm0, %r9
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; SSE41-NEXT: pextrq $1, %xmm3, %rdx
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; SSE41-NEXT: pextrq $1, %xmm1, %rax
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; SSE41-NEXT: andq %rdx, %rax
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; SSE41-NEXT: andq %r10, %rax
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; SSE41-NEXT: andq %r9, %rax
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; SSE41-NEXT: andq %rcx, %rax
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; SSE41-NEXT: andq %r8, %rax
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; SSE41-NEXT: cmpq $-1, %rax
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; SSE41-NEXT: cmovel %esi, %edi
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; SSE41-NEXT: movl %edi, %eax
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: vecsel512_ones:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovq %xmm1, %rax
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; AVX-NEXT: vmovq %xmm0, %r8
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; AVX-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX-NEXT: vmovq %xmm2, %rdx
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm3
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; AVX-NEXT: vmovq %xmm3, %rcx
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; AVX-NEXT: andq %rdx, %rcx
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; AVX-NEXT: andq %rax, %rcx
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; AVX-NEXT: vpextrq $1, %xmm1, %r10
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; AVX-NEXT: vpextrq $1, %xmm0, %r9
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; AVX-NEXT: vpextrq $1, %xmm2, %rdx
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; AVX-NEXT: vpextrq $1, %xmm3, %rax
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; AVX-NEXT: andq %rdx, %rax
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; AVX-NEXT: andq %r10, %rax
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; AVX-NEXT: andq %r9, %rax
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; AVX-NEXT: andq %rcx, %rax
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; AVX-NEXT: andq %r8, %rax
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; AVX-NEXT: cmpq $-1, %rax
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; AVX-NEXT: cmovel %esi, %edi
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; AVX-NEXT: movl %edi, %eax
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%t0 = bitcast <16 x i32> %input to i512
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%t1 = icmp ne i512 %t0, -1
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%t2 = select i1 %t1, i32 %a, i32 %b
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ret i32 %t2
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}
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