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Revert for Capstone:

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We want to know that the instruction is v8.
Because this is how it is defined in the ISA.

Revert "[ARM] Change CRC predicate to just HasCRC"

This reverts commit a82c106e57.
This commit is contained in:
Rot127 2024-11-07 11:53:38 -05:00 committed by Rot127
parent 92c98d24a3
commit c06b997485
6 changed files with 26 additions and 29 deletions
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2
llvm/lib/Target/ARM/ARMInstrInfo.td
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@ -4864,7 +4864,7 @@ class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
: AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
!strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
[(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
Requires<[IsARM, HasCRC]> {
Requires<[IsARM, HasV8, HasCRC]> {
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;

2
llvm/lib/Target/ARM/ARMInstrThumb2.td
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@ -3461,7 +3461,7 @@ class T2I_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
: T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary,
!strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"),
[(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>,
Requires<[IsThumb2, HasCRC]> {
Requires<[IsThumb2, HasV8, HasCRC]> {
let Inst{31-27} = 0b11111;
let Inst{26-21} = 0b010110;
let Inst{20} = C;

3
llvm/test/CodeGen/ARM/crc32.ll
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@ -1,7 +1,4 @@
; RUN: llc -mtriple=thumbv7 -mattr=+crc -o - %s | FileCheck %s
; RUN: llc -mtriple=thumbv8 -o - %s | FileCheck %s
; RUN: llc -mtriple=armv7 -mattr=+crc -o - %s | FileCheck %s
; RUN: llc -mtriple=armv8 -o - %s | FileCheck %s
define i32 @test_crc32b(i32 %cur, i8 %next) {
; CHECK-LABEL: test_crc32b:

12
llvm/test/MC/ARM/crc32-thumb.s
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@ -8,9 +8,9 @@
@ CHECK: crc32b r0, r1, r2 @ encoding: [0xc1,0xfa,0x82,0xf0]
@ CHECK: crc32h r0, r1, r2 @ encoding: [0xc1,0xfa,0x92,0xf0]
@ CHECK: crc32w r0, r1, r2 @ encoding: [0xc1,0xfa,0xa2,0xf0]
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
@ -22,9 +22,9 @@
@ CHECK: crc32cb r0, r1, r2 @ encoding: [0xd1,0xfa,0x82,0xf0]
@ CHECK: crc32ch r0, r1, r2 @ encoding: [0xd1,0xfa,0x92,0xf0]
@ CHECK: crc32cw r0, r1, r2 @ encoding: [0xd1,0xfa,0xa2,0xf0]
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc

12
llvm/test/MC/ARM/crc32.s
View File

@ -8,9 +8,9 @@
@ CHECK: crc32b r0, r1, r2 @ encoding: [0x42,0x00,0x01,0xe1]
@ CHECK: crc32h r0, r1, r2 @ encoding: [0x42,0x00,0x21,0xe1]
@ CHECK: crc32w r0, r1, r2 @ encoding: [0x42,0x00,0x41,0xe1]
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
@ -22,9 +22,9 @@
@ CHECK: crc32cb r0, r1, r2 @ encoding: [0x42,0x02,0x01,0xe1]
@ CHECK: crc32ch r0, r1, r2 @ encoding: [0x42,0x02,0x21,0xe1]
@ CHECK: crc32cw r0, r1, r2 @ encoding: [0x42,0x02,0x41,0xe1]
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc
@ CHECK-NOCRC: error: instruction requires: crc

24
llvm/test/MC/ARM/directive-arch_extension-crc.s
View File

@ -15,18 +15,18 @@
.type crc,%function
crc:
crc32b r0, r1, r2
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc armv8
crc32h r0, r1, r2
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc armv8
crc32w r0, r1, r2
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc armv8
crc32cb r0, r1, r2
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc armv8
crc32ch r0, r1, r2
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc armv8
crc32cw r0, r1, r2
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc armv8
.arch_extension nocrc
@ CHECK-V7: error: architectural extension 'crc' is not allowed for the current base architecture
@ -36,22 +36,22 @@ crc:
.type nocrc,%function
nocrc:
crc32b r0, r1, r2
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V8: error: instruction requires: crc
crc32h r0, r1, r2
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V8: error: instruction requires: crc
crc32w r0, r1, r2
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V8: error: instruction requires: crc
crc32cb r0, r1, r2
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V8: error: instruction requires: crc
crc32ch r0, r1, r2
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V8: error: instruction requires: crc
crc32cw r0, r1, r2
@ CHECK-V7: error: instruction requires: crc
@ CHECK-V7: error: instruction requires: crc armv8
@ CHECK-V8: error: instruction requires: crc