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https://github.com/capstone-engine/llvm-capstone.git
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[AMDGPU][DOC][NFC] Updated GFX10 assembler syntax description
The description has been updated to reflect AMDGPU MC changes: - enabled literals for src0 of v_fmaak_f*, v_fmamk_f*, v_madak_f32, v_madmk_f32; - enabled global_atomic_fcmpswap and global_atomic_fcmpswap_x2; - enabled dlc with flat_atomic* and global_atomic_*. Bug fixing and improvements: - enabled s_wait_idle; - enabled s_waitcnt_depctr; - added description of s_waitcnt_depctr syntactic sugar; - disabled SYSMSG_OP_HOST_TRAP_ACK (it is not supported on GFX10); - corrected description of lgkmcnt (accept values from 0 to 63).
This commit is contained in:
Dmitry Preobrazhensky
parent
0ac213667d
commit
c33770d87f
File diff suppressed because it is too large
Load Diff
@ -41,27 +41,27 @@ or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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Defined register *names* include:
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=================== ==========================================
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Name Description
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=================== ==========================================
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HW_REG_MODE Shader writeable mode bits.
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HW_REG_STATUS Shader read-only status.
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HW_REG_TRAPSTS Trap status.
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HW_REG_HW_ID1 Id of wave, simd, compute unit, etc.
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HW_REG_HW_ID2 Id of queue, pipeline, etc.
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HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
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HW_REG_LDS_ALLOC Per-wave LDS allocation.
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HW_REG_IB_STS Counters of outstanding instructions.
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HW_REG_SH_MEM_BASES Memory aperture.
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HW_REG_TBA_LO tba_lo register.
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HW_REG_TBA_HI tba_hi register.
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HW_REG_TMA_LO tma_lo register.
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HW_REG_TMA_HI tma_hi register.
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HW_REG_FLAT_SCR_LO flat_scratch_lo register.
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HW_REG_FLAT_SCR_HI flat_scratch_hi register.
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HW_REG_XNACK_MASK xnack_mask register.
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HW_REG_POPS_PACKER pops_packer register.
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=================== ==========================================
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==================== ==========================================
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Name Description
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==================== ==========================================
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HW_REG_MODE Shader writeable mode bits.
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HW_REG_STATUS Shader read-only status.
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HW_REG_TRAPSTS Trap status.
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HW_REG_HW_ID1 Id of wave, simd, compute unit, etc.
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HW_REG_HW_ID2 Id of queue, pipeline, etc.
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HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
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HW_REG_LDS_ALLOC Per-wave LDS allocation.
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HW_REG_IB_STS Counters of outstanding instructions.
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HW_REG_SH_MEM_BASES Memory aperture.
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HW_REG_TBA_LO tba_lo register.
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HW_REG_TBA_HI tba_hi register.
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HW_REG_TMA_LO tma_lo register.
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HW_REG_TMA_HI tma_hi register.
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HW_REG_FLAT_SCR_LO flat_scratch_lo register.
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HW_REG_FLAT_SCR_HI flat_scratch_hi register.
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HW_REG_XNACK_MASK xnack_mask register.
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HW_REG_POPS_PACKER pops_packer register.
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==================== ==========================================
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Examples:
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@ -1,13 +0,0 @@
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_imm16_2:
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imm16
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=====
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A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_imm16:
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.. _amdgpu_synid_gfx10_imm16_73139a:
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imm16
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=====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_imm16_1:
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.. _amdgpu_synid_gfx10_imm16_a04fb3:
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imm16
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=====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_m_1:
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.. _amdgpu_synid_gfx10_m_254bcb:
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m
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=
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_m:
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.. _amdgpu_synid_gfx10_m_f5d306:
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m
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=
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@ -47,29 +47,28 @@ or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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Each message type supports specific operations:
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=================== ========== ============================== ============ ==========
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Message name Message Id Supported Operations Operation Id Stream Id
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=================== ========== ============================== ============ ==========
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MSG_INTERRUPT 1 \- \- \-
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MSG_GS 2 GS_OP_CUT 1 Optional
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\ GS_OP_EMIT 2 Optional
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\ GS_OP_EMIT_CUT 3 Optional
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MSG_GS_DONE 3 GS_OP_NOP 0 \-
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\ GS_OP_CUT 1 Optional
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\ GS_OP_EMIT 2 Optional
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\ GS_OP_EMIT_CUT 3 Optional
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MSG_SAVEWAVE 4 \- \- \-
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MSG_STALL_WAVE_GEN 5 \- \- \-
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MSG_HALT_WAVES 6 \- \- \-
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MSG_ORDERED_PS_DONE 7 \- \- \-
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MSG_GS_ALLOC_REQ 9 \- \- \-
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MSG_GET_DOORBELL 10 \- \- \-
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MSG_GET_DDID 11 \- \- \-
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MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \-
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\ SYSMSG_OP_REG_RD 2 \-
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\ SYSMSG_OP_HOST_TRAP_ACK 3 \-
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\ SYSMSG_OP_TTRACE_PC 4 \-
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=================== ========== ============================== ============ ==========
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====================== ========== ============================== ============ ==========
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Message name Message Id Supported Operations Operation Id Stream Id
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====================== ========== ============================== ============ ==========
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MSG_INTERRUPT 1 \- \- \-
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MSG_GS 2 GS_OP_CUT 1 Optional
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\ GS_OP_EMIT 2 Optional
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\ GS_OP_EMIT_CUT 3 Optional
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MSG_GS_DONE 3 GS_OP_NOP 0 \-
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\ GS_OP_CUT 1 Optional
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\ GS_OP_EMIT 2 Optional
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\ GS_OP_EMIT_CUT 3 Optional
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MSG_SAVEWAVE 4 \- \- \-
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MSG_STALL_WAVE_GEN 5 \- \- \-
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MSG_HALT_WAVES 6 \- \- \-
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MSG_ORDERED_PS_DONE 7 \- \- \-
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MSG_GS_ALLOC_REQ 9 \- \- \-
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MSG_GET_DOORBELL 10 \- \- \-
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MSG_GET_DDID 11 \- \- \-
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MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \-
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\ SYSMSG_OP_REG_RD 2 \-
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\ SYSMSG_OP_TTRACE_PC 4 \-
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====================== ========== ============================== ============ ==========
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*Sendmsg* arguments are validated depending on how *type* value is specified:
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@ -5,14 +5,14 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_saddr:
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.. _amdgpu_synid_gfx10_saddr_beaa25:
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saddr
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=====
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An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
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See :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>` for description of available addressing modes.
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See :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>` for description of available addressing modes.
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*Size:* 2 dwords.
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@ -5,14 +5,14 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_saddr_1:
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.. _amdgpu_synid_gfx10_saddr_da2a8a:
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saddr
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=====
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An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
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Either this operand or :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>` must be set to :ref:`off<amdgpu_synid_off>`.
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Either this operand or :ref:`vaddr<amdgpu_synid_gfx10_vaddr_76b997>` must be set to :ref:`off<amdgpu_synid_off>`.
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*Size:* 1 dword.
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sbase_1:
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.. _amdgpu_synid_gfx10_sbase_010ce0:
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sbase
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=====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sbase:
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.. _amdgpu_synid_gfx10_sbase_020892:
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sbase
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=====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sbase_2:
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.. _amdgpu_synid_gfx10_sbase_b2d796:
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sbase
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=====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sdata:
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.. _amdgpu_synid_gfx10_sdata_3d2ab7:
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sdata
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=====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sdata_3:
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.. _amdgpu_synid_gfx10_sdata_6fbc49:
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sdata
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=====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sdata_5:
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.. _amdgpu_synid_gfx10_sdata_7cbd60:
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sdata
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=====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sdata_1:
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.. _amdgpu_synid_gfx10_sdata_7e874d:
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sdata
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=====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sdata_4:
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.. _amdgpu_synid_gfx10_sdata_81ba27:
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sdata
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=====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sdata_2:
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.. _amdgpu_synid_gfx10_sdata_c6aec1:
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sdata
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=====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sdst_4:
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.. _amdgpu_synid_gfx10_sdst_0804b1:
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sdst
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====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sdst_8:
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.. _amdgpu_synid_gfx10_sdst_2e4c2a:
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sdst
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====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sdst_5:
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.. _amdgpu_synid_gfx10_sdst_362c37:
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sdst
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====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sdst:
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.. _amdgpu_synid_gfx10_sdst_3759f6:
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sdst
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====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sdst_3:
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.. _amdgpu_synid_gfx10_sdst_386c33:
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sdst
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====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sdst_2:
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.. _amdgpu_synid_gfx10_sdst_3bc700:
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sdst
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====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sdst_1:
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.. _amdgpu_synid_gfx10_sdst_54e16e:
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sdst
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====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sdst_6:
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.. _amdgpu_synid_gfx10_sdst_8078f5:
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sdst
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====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_sdst_7:
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.. _amdgpu_synid_gfx10_sdst_ea3f10:
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sdst
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====
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@ -5,10 +5,10 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_simm32_2:
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.. _amdgpu_synid_gfx10_simm32_6f0844:
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simm32
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======
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A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
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The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`.
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The value is converted to *f32* as described :ref:`here<amdgpu_synid_conv>`.
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_simm32:
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.. _amdgpu_synid_gfx10_simm32_a3e80c:
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simm32
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======
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@ -5,10 +5,10 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_simm32_1:
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.. _amdgpu_synid_gfx10_simm32_be0c1c:
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simm32
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======
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A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
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The value is converted to *f16* as described :ref:`here<amdgpu_synid_fp_conv>`.
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The value is converted to *f16* as described :ref:`here<amdgpu_synid_conv>`.
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_soffset_2:
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.. _amdgpu_synid_gfx10_soffset_59fade:
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soffset
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=======
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_soffset:
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.. _amdgpu_synid_gfx10_soffset_b556e6:
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soffset
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=======
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_soffset_1:
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.. _amdgpu_synid_gfx10_soffset_c40a5a:
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soffset
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=======
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_src:
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.. _amdgpu_synid_gfx10_src_37d670:
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src
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===
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_src_5:
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.. _amdgpu_synid_gfx10_src_516946:
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src
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===
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@ -1,17 +0,0 @@
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_src_7:
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src
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===
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Instruction input.
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*Size:* 1 dword.
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*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_src_2:
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.. _amdgpu_synid_gfx10_src_823582:
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src
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===
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx10_src_8:
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.. _amdgpu_synid_gfx10_src_c27036:
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src
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===
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_src_6:
|
||||
.. _amdgpu_synid_gfx10_src_cf1cda:
|
||||
|
||||
src
|
||||
===
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_src_3:
|
||||
.. _amdgpu_synid_gfx10_src_d5cd94:
|
||||
|
||||
src
|
||||
===
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_src_1:
|
||||
.. _amdgpu_synid_gfx10_src_e0345d:
|
||||
|
||||
src
|
||||
===
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_src_4:
|
||||
.. _amdgpu_synid_gfx10_src_e9e6db:
|
||||
|
||||
src
|
||||
===
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_srsrc:
|
||||
.. _amdgpu_synid_gfx10_srsrc_cf7132:
|
||||
|
||||
srsrc
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_srsrc_1:
|
||||
.. _amdgpu_synid_gfx10_srsrc_e73d16:
|
||||
|
||||
srsrc
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_ssrc_8:
|
||||
.. _amdgpu_synid_gfx10_ssrc_054e2a:
|
||||
|
||||
ssrc
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_ssrc_1:
|
||||
.. _amdgpu_synid_gfx10_ssrc_2a042f:
|
||||
|
||||
ssrc
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_ssrc_5:
|
||||
.. _amdgpu_synid_gfx10_ssrc_3ec588:
|
||||
|
||||
ssrc
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_ssrc_4:
|
||||
.. _amdgpu_synid_gfx10_ssrc_460c63:
|
||||
|
||||
ssrc
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_ssrc_7:
|
||||
.. _amdgpu_synid_gfx10_ssrc_48e8e7:
|
||||
|
||||
ssrc
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_ssrc_2:
|
||||
.. _amdgpu_synid_gfx10_ssrc_6fbc49:
|
||||
|
||||
ssrc
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_ssrc:
|
||||
.. _amdgpu_synid_gfx10_ssrc_7da351:
|
||||
|
||||
ssrc
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_ssrc_3:
|
||||
.. _amdgpu_synid_gfx10_ssrc_81ba27:
|
||||
|
||||
ssrc
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_ssrc_6:
|
||||
.. _amdgpu_synid_gfx10_ssrc_9a4448:
|
||||
|
||||
ssrc
|
||||
====
|
||||
@ -12,13 +12,13 @@ tgt
|
||||
|
||||
An export target:
|
||||
|
||||
============== ===================================
|
||||
Syntax Description
|
||||
============== ===================================
|
||||
pos{0..4} Copy vertex position 0..4.
|
||||
param{0..31} Copy vertex parameter 0..31.
|
||||
mrt{0..7} Copy pixel color to the MRTs 0..7.
|
||||
mrtz Copy pixel depth (Z) data.
|
||||
prim Copy primitive (connectivity) data.
|
||||
null Copy nothing.
|
||||
============== ===================================
|
||||
================== ===================================
|
||||
Syntax Description
|
||||
================== ===================================
|
||||
pos{0..4} Copy vertex position 0..4.
|
||||
param{0..31} Copy vertex parameter 0..31.
|
||||
mrt{0..7} Copy pixel color to the MRTs 0..7.
|
||||
mrtz Copy pixel depth (Z) data.
|
||||
prim Copy primitive (connectivity) data.
|
||||
null Copy nothing.
|
||||
================== ===================================
|
||||
|
||||
@ -1,20 +0,0 @@
|
||||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vaddr_2:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
||||
A 64-bit flat global address or a 32-bit offset depending on addressing mode:
|
||||
|
||||
* Address = :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid_gfx10_saddr>` set to :ref:`off<amdgpu_synid_off>`.
|
||||
* Address = :ref:`saddr<amdgpu_synid_gfx10_saddr>` + :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid_gfx10_saddr>` is not :ref:`off<amdgpu_synid_off>`.
|
||||
|
||||
*Size:* 1 or 2 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
@ -5,14 +5,14 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vaddr_3:
|
||||
.. _amdgpu_synid_gfx10_vaddr_76b997:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
||||
An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
|
||||
|
||||
Either this operand or :ref:`saddr<amdgpu_synid_gfx10_saddr_1>` must be set to :ref:`off<amdgpu_synid_off>`.
|
||||
Either this operand or :ref:`saddr<amdgpu_synid_gfx10_saddr_da2a8a>` must be set to :ref:`off<amdgpu_synid_off>`.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
20
llvm/docs/AMDGPU/gfx10_vaddr_9aeece.rst
Normal file
20
llvm/docs/AMDGPU/gfx10_vaddr_9aeece.rst
Normal file
@ -0,0 +1,20 @@
|
||||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vaddr_9aeece:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
||||
A 64-bit flat global address or a 32-bit offset depending on addressing mode:
|
||||
|
||||
* Address = :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` set to :ref:`off<amdgpu_synid_off>`.
|
||||
* Address = :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` + :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid_gfx10_vaddr_9aeece>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid_gfx10_saddr_beaa25>` is not :ref:`off<amdgpu_synid_off>`.
|
||||
|
||||
*Size:* 1 or 2 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vaddr_1:
|
||||
.. _amdgpu_synid_gfx10_vaddr_9f7133:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vaddr_5:
|
||||
.. _amdgpu_synid_gfx10_vaddr_b73dc0:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vaddr_4:
|
||||
.. _amdgpu_synid_gfx10_vaddr_cdc744:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vaddr:
|
||||
.. _amdgpu_synid_gfx10_vaddr_f20ee4:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdata0:
|
||||
.. _amdgpu_synid_gfx10_vdata0_6802ce:
|
||||
|
||||
vdata0
|
||||
======
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdata0_1:
|
||||
.. _amdgpu_synid_gfx10_vdata0_fd235e:
|
||||
|
||||
vdata0
|
||||
======
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdata1:
|
||||
.. _amdgpu_synid_gfx10_vdata1_6802ce:
|
||||
|
||||
vdata1
|
||||
======
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdata1_1:
|
||||
.. _amdgpu_synid_gfx10_vdata1_fd235e:
|
||||
|
||||
vdata1
|
||||
======
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdata_6:
|
||||
.. _amdgpu_synid_gfx10_vdata_15d255:
|
||||
|
||||
vdata
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdata_4:
|
||||
.. _amdgpu_synid_gfx10_vdata_325b78:
|
||||
|
||||
vdata
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdata_5:
|
||||
.. _amdgpu_synid_gfx10_vdata_4d8ecf:
|
||||
|
||||
vdata
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdata_3:
|
||||
.. _amdgpu_synid_gfx10_vdata_56f215:
|
||||
|
||||
vdata
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdata:
|
||||
.. _amdgpu_synid_gfx10_vdata_6802ce:
|
||||
|
||||
vdata
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdata_10:
|
||||
.. _amdgpu_synid_gfx10_vdata_87fb90:
|
||||
|
||||
vdata
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdata_9:
|
||||
.. _amdgpu_synid_gfx10_vdata_b2a787:
|
||||
|
||||
vdata
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdata_7:
|
||||
.. _amdgpu_synid_gfx10_vdata_c08393:
|
||||
|
||||
vdata
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdata_8:
|
||||
.. _amdgpu_synid_gfx10_vdata_c61803:
|
||||
|
||||
vdata
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdata_2:
|
||||
.. _amdgpu_synid_gfx10_vdata_e016a1:
|
||||
|
||||
vdata
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdata_1:
|
||||
.. _amdgpu_synid_gfx10_vdata_fd235e:
|
||||
|
||||
vdata
|
||||
=====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdst_7:
|
||||
.. _amdgpu_synid_gfx10_vdst_3d7dcf:
|
||||
|
||||
vdst
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdst_5:
|
||||
.. _amdgpu_synid_gfx10_vdst_463513:
|
||||
|
||||
vdst
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdst_8:
|
||||
.. _amdgpu_synid_gfx10_vdst_473a69:
|
||||
|
||||
vdst
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdst_6:
|
||||
.. _amdgpu_synid_gfx10_vdst_48d3a8:
|
||||
|
||||
vdst
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdst_3:
|
||||
.. _amdgpu_synid_gfx10_vdst_48e42f:
|
||||
|
||||
vdst
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdst_9:
|
||||
.. _amdgpu_synid_gfx10_vdst_5d50a1:
|
||||
|
||||
vdst
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdst_2:
|
||||
.. _amdgpu_synid_gfx10_vdst_69a144:
|
||||
|
||||
vdst
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdst_13:
|
||||
.. _amdgpu_synid_gfx10_vdst_719833:
|
||||
|
||||
vdst
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdst:
|
||||
.. _amdgpu_synid_gfx10_vdst_89680f:
|
||||
|
||||
vdst
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdst_11:
|
||||
.. _amdgpu_synid_gfx10_vdst_a49b76:
|
||||
|
||||
vdst
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdst_1:
|
||||
.. _amdgpu_synid_gfx10_vdst_bdb32f:
|
||||
|
||||
vdst
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdst_4:
|
||||
.. _amdgpu_synid_gfx10_vdst_d0dc43:
|
||||
|
||||
vdst
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdst_10:
|
||||
.. _amdgpu_synid_gfx10_vdst_d7c57e:
|
||||
|
||||
vdst
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vdst_12:
|
||||
.. _amdgpu_synid_gfx10_vdst_f47754:
|
||||
|
||||
vdst
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vsrc_1:
|
||||
.. _amdgpu_synid_gfx10_vsrc_533a4e:
|
||||
|
||||
vsrc
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vsrc:
|
||||
.. _amdgpu_synid_gfx10_vsrc_6802ce:
|
||||
|
||||
vsrc
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vsrc_2:
|
||||
.. _amdgpu_synid_gfx10_vsrc_e016a1:
|
||||
|
||||
vsrc
|
||||
====
|
||||
@ -5,7 +5,7 @@
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_vsrc_3:
|
||||
.. _amdgpu_synid_gfx10_vsrc_fd235e:
|
||||
|
||||
vsrc
|
||||
====
|
||||
@ -19,7 +19,7 @@ The bits of this operand have the following meaning:
|
||||
========== ========= ================================================ ============
|
||||
15:14 3:0 VM_CNT: vector memory operations count. 0..63
|
||||
\- 6:4 EXP_CNT: export count. 0..7
|
||||
\- 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15
|
||||
\- 13:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..63
|
||||
========== ========= ================================================ ============
|
||||
|
||||
This operand may be specified as one of the following:
|
||||
|
||||
39
llvm/docs/AMDGPU/gfx10_waitcnt_depctr.rst
Normal file
39
llvm/docs/AMDGPU/gfx10_waitcnt_depctr.rst
Normal file
@ -0,0 +1,39 @@
|
||||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx10_waitcnt_depctr:
|
||||
|
||||
waitcnt_depctr
|
||||
==============
|
||||
|
||||
Dependency counters to wait for.
|
||||
|
||||
This operand may be specified as one of the following:
|
||||
|
||||
* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
|
||||
* A combination of *symbolic values* described below.
|
||||
|
||||
======================== ======================== ================ =================
|
||||
Syntax Description Valid *N* Values Default *N* Value
|
||||
======================== ======================== ================ =================
|
||||
depctr_sa_sdst(<*N*>) Wait for SA_SDST <= N 0..1 1
|
||||
depctr_va_vdst(<*N*>) Wait for VA_VDST <= N 0..15 15
|
||||
depctr_va_sdst(<*N*>) Wait for VA_SDST <= N 0..7 7
|
||||
depctr_va_ssrc(<*N*>) Wait for VA_SSRC <= N 0..1 1
|
||||
depctr_va_vcc(<*N*>) Wait for VA_VCC <= N 0..1 1
|
||||
depctr_vm_vsrc(<*N*>) Wait for VM_VSRC <= N 0..7 7
|
||||
======================== ======================== ================ =================
|
||||
|
||||
These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators.
|
||||
|
||||
Examples:
|
||||
|
||||
.. parsed-literal::
|
||||
|
||||
s_waitcnt_depctr depctr_sa_sdst(0) depctr_va_vdst(0)
|
||||
s_waitcnt_depctr depctr_sa_sdst(1) & depctr_va_vdst(1)
|
||||
s_waitcnt_depctr depctr_va_vdst(3), depctr_va_sdst(5)
|
||||
Loading…
x
Reference in New Issue
Block a user