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[libunwind][MIPS] Support MIPS floating-point registers for hard-float ABIs.

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Summary:
For MIPS ABIs with 64-bit floating point registers including newabi
and O32 with 64-bit floating point registers, just save and restore the
32 floating-point registers as doubles.

For O32 MIPS with 32-bit floating-point registers, save and restore the
individual floating-point registers as "plain" registers.  These registers
are encoded as floats rather than doubles, but the DWARF unwinder
assumes that floating-point registers are stored as doubles when reading
them from memory (via AddressSpace::getDouble()).  Treating the
registers as "normal" registers instead causes the DWARF unwinder to
fetch them from memory as a 32-bit register.  This does mean that for
O32 with 32-bit floating-point registers unw_get_fpreg() and
unw_set_fpreg() do not work.  One would have to use unw_get_reg()
and unw_set_reg() instead.  However, DWARF unwinding works
correctly as the DWARF CFI emits records for individual 32-bit
floating-point registers even when they are treated as doubles stored
in paired registers.  If the lack of unw_get/set_fpreg() becomes a pressing
need in the future for O32 MIPS we could add in special handling to
make it work.

Reviewers: sdardis, compnerd

Reviewed By: sdardis

Differential Revision: https://reviews.llvm.org/D41968

llvm-svn: 332414
This commit is contained in:
John Baldwin 2018-05-15 22:44:56 +00:00
parent 85d3a702da
commit c3f240f7dc
6 changed files with 439 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
libunwind/include/__libunwind_config.h
View File

@ -71,18 +71,33 @@
# define _LIBUNWIND_CURSOR_SIZE 24 # define _LIBUNWIND_CURSOR_SIZE 24
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K # define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K
# elif defined(__mips__) # elif defined(__mips__)
# if defined(_ABIO32) && _MIPS_SIM == _ABIO32 && defined(__mips_soft_float) # if defined(_ABIO32) && _MIPS_SIM == _ABIO32
# define _LIBUNWIND_TARGET_MIPS_O32 1 # define _LIBUNWIND_TARGET_MIPS_O32 1
# define _LIBUNWIND_CONTEXT_SIZE 18 # if defined(__mips_hard_float)
# define _LIBUNWIND_CURSOR_SIZE 24 # define _LIBUNWIND_CONTEXT_SIZE 50
# elif defined(_ABIN32) && _MIPS_SIM == _ABIN32 && defined(__mips_soft_float) # define _LIBUNWIND_CURSOR_SIZE 57
# else
# define _LIBUNWIND_CONTEXT_SIZE 18
# define _LIBUNWIND_CURSOR_SIZE 24
# endif
# elif defined(_ABIN32) && _MIPS_SIM == _ABIN32
# define _LIBUNWIND_TARGET_MIPS_NEWABI 1 # define _LIBUNWIND_TARGET_MIPS_NEWABI 1
# define _LIBUNWIND_CONTEXT_SIZE 35 # if defined(__mips_hard_float)
# define _LIBUNWIND_CURSOR_SIZE 42 # define _LIBUNWIND_CONTEXT_SIZE 67
# elif defined(_ABI64) && _MIPS_SIM == _ABI64 && defined(__mips_soft_float) # define _LIBUNWIND_CURSOR_SIZE 74
# else
# define _LIBUNWIND_CONTEXT_SIZE 35
# define _LIBUNWIND_CURSOR_SIZE 42
# endif
# elif defined(_ABI64) && _MIPS_SIM == _ABI64
# define _LIBUNWIND_TARGET_MIPS_NEWABI 1 # define _LIBUNWIND_TARGET_MIPS_NEWABI 1
# define _LIBUNWIND_CONTEXT_SIZE 35 # if defined(__mips_hard_float)
# define _LIBUNWIND_CURSOR_SIZE 47 # define _LIBUNWIND_CONTEXT_SIZE 67
# define _LIBUNWIND_CURSOR_SIZE 79
# else
# define _LIBUNWIND_CONTEXT_SIZE 35
# define _LIBUNWIND_CURSOR_SIZE 47
# endif
# else # else
# error "Unsupported MIPS ABI and/or environment" # error "Unsupported MIPS ABI and/or environment"
# endif # endif

32
libunwind/include/libunwind.h
View File

@ -781,6 +781,38 @@ enum {
UNW_MIPS_R29 = 29, UNW_MIPS_R29 = 29,
UNW_MIPS_R30 = 30, UNW_MIPS_R30 = 30,
UNW_MIPS_R31 = 31, UNW_MIPS_R31 = 31,
UNW_MIPS_F0 = 32,
UNW_MIPS_F1 = 33,
UNW_MIPS_F2 = 34,
UNW_MIPS_F3 = 35,
UNW_MIPS_F4 = 36,
UNW_MIPS_F5 = 37,
UNW_MIPS_F6 = 38,
UNW_MIPS_F7 = 39,
UNW_MIPS_F8 = 40,
UNW_MIPS_F9 = 41,
UNW_MIPS_F10 = 42,
UNW_MIPS_F11 = 43,
UNW_MIPS_F12 = 44,
UNW_MIPS_F13 = 45,
UNW_MIPS_F14 = 46,
UNW_MIPS_F15 = 47,
UNW_MIPS_F16 = 48,
UNW_MIPS_F17 = 49,
UNW_MIPS_F18 = 50,
UNW_MIPS_F19 = 51,
UNW_MIPS_F20 = 52,
UNW_MIPS_F21 = 53,
UNW_MIPS_F22 = 54,
UNW_MIPS_F23 = 55,
UNW_MIPS_F24 = 56,
UNW_MIPS_F25 = 57,
UNW_MIPS_F26 = 58,
UNW_MIPS_F27 = 59,
UNW_MIPS_F28 = 60,
UNW_MIPS_F29 = 61,
UNW_MIPS_F30 = 62,
UNW_MIPS_F31 = 63,
UNW_MIPS_HI = 64, UNW_MIPS_HI = 64,
UNW_MIPS_LO = 65, UNW_MIPS_LO = 65,
}; };

212
libunwind/src/Registers.hpp
View File

@ -2718,6 +2718,14 @@ private:
}; };
mips_o32_thread_state_t _registers; mips_o32_thread_state_t _registers;
#ifdef __mips_hard_float
/// O32 with 32-bit floating point registers only uses half of this
/// space. However, using the same layout for 32-bit vs 64-bit
/// floating point registers results in a single context size for
/// O32 with hard float.
uint32_t _padding;
double _floats[32];
#endif
}; };
inline Registers_mips_o32::Registers_mips_o32(const void *registers) { inline Registers_mips_o32::Registers_mips_o32(const void *registers) {
@ -2744,13 +2752,28 @@ inline bool Registers_mips_o32::validRegister(int regNum) const {
return true; return true;
if (regNum == UNW_MIPS_LO) if (regNum == UNW_MIPS_LO)
return true; return true;
// FIXME: Hard float, DSP accumulator registers, MSA registers #if defined(__mips_hard_float) && __mips_fpr == 32
if (regNum >= UNW_MIPS_F0 && regNum <= UNW_MIPS_F31)
return true;
#endif
// FIXME: DSP accumulator registers, MSA registers
return false; return false;
} }
inline uint32_t Registers_mips_o32::getRegister(int regNum) const { inline uint32_t Registers_mips_o32::getRegister(int regNum) const {
if (regNum >= UNW_MIPS_R0 && regNum <= UNW_MIPS_R31) if (regNum >= UNW_MIPS_R0 && regNum <= UNW_MIPS_R31)
return _registers.__r[regNum - UNW_MIPS_R0]; return _registers.__r[regNum - UNW_MIPS_R0];
#if defined(__mips_hard_float) && __mips_fpr == 32
if (regNum >= UNW_MIPS_F0 && regNum <= UNW_MIPS_F31) {
uint32_t *p;
if (regNum % 2 == 0)
p = (uint32_t *)&_floats[regNum - UNW_MIPS_F0];
else
p = (uint32_t *)&_floats[(regNum - 1) - UNW_MIPS_F0] + 1;
return *p;
}
#endif
switch (regNum) { switch (regNum) {
case UNW_REG_IP: case UNW_REG_IP:
@ -2770,6 +2793,18 @@ inline void Registers_mips_o32::setRegister(int regNum, uint32_t value) {
_registers.__r[regNum - UNW_MIPS_R0] = value; _registers.__r[regNum - UNW_MIPS_R0] = value;
return; return;
} }
#if defined(__mips_hard_float) && __mips_fpr == 32
if (regNum >= UNW_MIPS_F0 && regNum <= UNW_MIPS_F31) {
uint32_t *p;
if (regNum % 2 == 0)
p = (uint32_t *)&_floats[regNum - UNW_MIPS_F0];
else
p = (uint32_t *)&_floats[(regNum - 1) - UNW_MIPS_F0] + 1;
*p = value;
return;
}
#endif
switch (regNum) { switch (regNum) {
case UNW_REG_IP: case UNW_REG_IP:
@ -2788,17 +2823,31 @@ inline void Registers_mips_o32::setRegister(int regNum, uint32_t value) {
_LIBUNWIND_ABORT("unsupported mips_o32 register"); _LIBUNWIND_ABORT("unsupported mips_o32 register");
} }
inline bool Registers_mips_o32::validFloatRegister(int /* regNum */) const { inline bool Registers_mips_o32::validFloatRegister(int regNum) const {
#if defined(__mips_hard_float) && __mips_fpr == 64
if (regNum >= UNW_MIPS_F0 && regNum <= UNW_MIPS_F31)
return true;
#endif
return false; return false;
} }
inline double Registers_mips_o32::getFloatRegister(int /* regNum */) const { inline double Registers_mips_o32::getFloatRegister(int regNum) const {
#if defined(__mips_hard_float) && __mips_fpr == 64
assert(validFloatRegister(regNum));
return _floats[regNum - UNW_MIPS_F0];
#else
_LIBUNWIND_ABORT("mips_o32 float support not implemented"); _LIBUNWIND_ABORT("mips_o32 float support not implemented");
#endif
} }
inline void Registers_mips_o32::setFloatRegister(int /* regNum */, inline void Registers_mips_o32::setFloatRegister(int regNum,
double /* value */) { double value) {
#if defined(__mips_hard_float) && __mips_fpr == 64
assert(validFloatRegister(regNum));
_floats[regNum - UNW_MIPS_F0] = value;
#else
_LIBUNWIND_ABORT("mips_o32 float support not implemented"); _LIBUNWIND_ABORT("mips_o32 float support not implemented");
#endif
} }
inline bool Registers_mips_o32::validVectorRegister(int /* regNum */) const { inline bool Registers_mips_o32::validVectorRegister(int /* regNum */) const {
@ -2879,6 +2928,70 @@ inline const char *Registers_mips_o32::getRegisterName(int regNum) {
return "$30"; return "$30";
case UNW_MIPS_R31: case UNW_MIPS_R31:
return "$31"; return "$31";
case UNW_MIPS_F0:
return "$f0";
case UNW_MIPS_F1:
return "$f1";
case UNW_MIPS_F2:
return "$f2";
case UNW_MIPS_F3:
return "$f3";
case UNW_MIPS_F4:
return "$f4";
case UNW_MIPS_F5:
return "$f5";
case UNW_MIPS_F6:
return "$f6";
case UNW_MIPS_F7:
return "$f7";
case UNW_MIPS_F8:
return "$f8";
case UNW_MIPS_F9:
return "$f9";
case UNW_MIPS_F10:
return "$f10";
case UNW_MIPS_F11:
return "$f11";
case UNW_MIPS_F12:
return "$f12";
case UNW_MIPS_F13:
return "$f13";
case UNW_MIPS_F14:
return "$f14";
case UNW_MIPS_F15:
return "$f15";
case UNW_MIPS_F16:
return "$f16";
case UNW_MIPS_F17:
return "$f17";
case UNW_MIPS_F18:
return "$f18";
case UNW_MIPS_F19:
return "$f19";
case UNW_MIPS_F20:
return "$f20";
case UNW_MIPS_F21:
return "$f21";
case UNW_MIPS_F22:
return "$f22";
case UNW_MIPS_F23:
return "$f23";
case UNW_MIPS_F24:
return "$f24";
case UNW_MIPS_F25:
return "$f25";
case UNW_MIPS_F26:
return "$f26";
case UNW_MIPS_F27:
return "$f27";
case UNW_MIPS_F28:
return "$f28";
case UNW_MIPS_F29:
return "$f29";
case UNW_MIPS_F30:
return "$f30";
case UNW_MIPS_F31:
return "$f31";
case UNW_MIPS_HI: case UNW_MIPS_HI:
return "$hi"; return "$hi";
case UNW_MIPS_LO: case UNW_MIPS_LO:
@ -2924,6 +3037,9 @@ private:
}; };
mips_newabi_thread_state_t _registers; mips_newabi_thread_state_t _registers;
#ifdef __mips_hard_float
double _floats[32];
#endif
}; };
inline Registers_mips_newabi::Registers_mips_newabi(const void *registers) { inline Registers_mips_newabi::Registers_mips_newabi(const void *registers) {
@ -2994,17 +3110,31 @@ inline void Registers_mips_newabi::setRegister(int regNum, uint64_t value) {
_LIBUNWIND_ABORT("unsupported mips_newabi register"); _LIBUNWIND_ABORT("unsupported mips_newabi register");
} }
inline bool Registers_mips_newabi::validFloatRegister(int /* regNum */) const { inline bool Registers_mips_newabi::validFloatRegister(int regNum) const {
#ifdef __mips_hard_float
if (regNum >= UNW_MIPS_F0 && regNum <= UNW_MIPS_F31)
return true;
#endif
return false; return false;
} }
inline double Registers_mips_newabi::getFloatRegister(int /* regNum */) const { inline double Registers_mips_newabi::getFloatRegister(int regNum) const {
#ifdef __mips_hard_float
assert(validFloatRegister(regNum));
return _floats[regNum - UNW_MIPS_F0];
#else
_LIBUNWIND_ABORT("mips_newabi float support not implemented"); _LIBUNWIND_ABORT("mips_newabi float support not implemented");
#endif
} }
inline void Registers_mips_newabi::setFloatRegister(int /* regNum */, inline void Registers_mips_newabi::setFloatRegister(int regNum,
double /* value */) { double value) {
#ifdef __mips_hard_float
assert(validFloatRegister(regNum));
_floats[regNum - UNW_MIPS_F0] = value;
#else
_LIBUNWIND_ABORT("mips_newabi float support not implemented"); _LIBUNWIND_ABORT("mips_newabi float support not implemented");
#endif
} }
inline bool Registers_mips_newabi::validVectorRegister(int /* regNum */) const { inline bool Registers_mips_newabi::validVectorRegister(int /* regNum */) const {
@ -3085,6 +3215,70 @@ inline const char *Registers_mips_newabi::getRegisterName(int regNum) {
return "$30"; return "$30";
case UNW_MIPS_R31: case UNW_MIPS_R31:
return "$31"; return "$31";
case UNW_MIPS_F0:
return "$f0";
case UNW_MIPS_F1:
return "$f1";
case UNW_MIPS_F2:
return "$f2";
case UNW_MIPS_F3:
return "$f3";
case UNW_MIPS_F4:
return "$f4";
case UNW_MIPS_F5:
return "$f5";
case UNW_MIPS_F6:
return "$f6";
case UNW_MIPS_F7:
return "$f7";
case UNW_MIPS_F8:
return "$f8";
case UNW_MIPS_F9:
return "$f9";
case UNW_MIPS_F10:
return "$f10";
case UNW_MIPS_F11:
return "$f11";
case UNW_MIPS_F12:
return "$f12";
case UNW_MIPS_F13:
return "$f13";
case UNW_MIPS_F14:
return "$f14";
case UNW_MIPS_F15:
return "$f15";
case UNW_MIPS_F16:
return "$f16";
case UNW_MIPS_F17:
return "$f17";
case UNW_MIPS_F18:
return "$f18";
case UNW_MIPS_F19:
return "$f19";
case UNW_MIPS_F20:
return "$f20";
case UNW_MIPS_F21:
return "$f21";
case UNW_MIPS_F22:
return "$f22";
case UNW_MIPS_F23:
return "$f23";
case UNW_MIPS_F24:
return "$f24";
case UNW_MIPS_F25:
return "$f25";
case UNW_MIPS_F26:
return "$f26";
case UNW_MIPS_F27:
return "$f27";
case UNW_MIPS_F28:
return "$f28";
case UNW_MIPS_F29:
return "$f29";
case UNW_MIPS_F30:
return "$f30";
case UNW_MIPS_F31:
return "$f31";
case UNW_MIPS_HI: case UNW_MIPS_HI:
return "$hi"; return "$hi";
case UNW_MIPS_LO: case UNW_MIPS_LO:

92
libunwind/src/UnwindRegistersRestore.S
View File

@ -799,8 +799,7 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind14Registers_or1k6jumptoEv)
l.jr r9 l.jr r9
l.nop l.nop
#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32 && \ #elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32
defined(__mips_soft_float)
// //
// void libunwind::Registers_mips_o32::jumpto() // void libunwind::Registers_mips_o32::jumpto()
@ -813,6 +812,59 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv)
.set noat .set noat
.set noreorder .set noreorder
.set nomacro .set nomacro
#ifdef __mips_hard_float
#if __mips_fpr == 32
ldc1 $f0, (4 * 36 + 8 * 0)($4)
ldc1 $f2, (4 * 36 + 8 * 2)($4)
ldc1 $f4, (4 * 36 + 8 * 4)($4)
ldc1 $f6, (4 * 36 + 8 * 6)($4)
ldc1 $f8, (4 * 36 + 8 * 8)($4)
ldc1 $f10, (4 * 36 + 8 * 10)($4)
ldc1 $f12, (4 * 36 + 8 * 12)($4)
ldc1 $f14, (4 * 36 + 8 * 14)($4)
ldc1 $f16, (4 * 36 + 8 * 16)($4)
ldc1 $f18, (4 * 36 + 8 * 18)($4)
ldc1 $f20, (4 * 36 + 8 * 20)($4)
ldc1 $f22, (4 * 36 + 8 * 22)($4)
ldc1 $f24, (4 * 36 + 8 * 24)($4)
ldc1 $f26, (4 * 36 + 8 * 26)($4)
ldc1 $f28, (4 * 36 + 8 * 28)($4)
ldc1 $f30, (4 * 36 + 8 * 30)($4)
#else
ldc1 $f0, (4 * 36 + 8 * 0)($4)
ldc1 $f1, (4 * 36 + 8 * 1)($4)
ldc1 $f2, (4 * 36 + 8 * 2)($4)
ldc1 $f3, (4 * 36 + 8 * 3)($4)
ldc1 $f4, (4 * 36 + 8 * 4)($4)
ldc1 $f5, (4 * 36 + 8 * 5)($4)
ldc1 $f6, (4 * 36 + 8 * 6)($4)
ldc1 $f7, (4 * 36 + 8 * 7)($4)
ldc1 $f8, (4 * 36 + 8 * 8)($4)
ldc1 $f9, (4 * 36 + 8 * 9)($4)
ldc1 $f10, (4 * 36 + 8 * 10)($4)
ldc1 $f11, (4 * 36 + 8 * 11)($4)
ldc1 $f12, (4 * 36 + 8 * 12)($4)
ldc1 $f13, (4 * 36 + 8 * 13)($4)
ldc1 $f14, (4 * 36 + 8 * 14)($4)
ldc1 $f15, (4 * 36 + 8 * 15)($4)
ldc1 $f16, (4 * 36 + 8 * 16)($4)
ldc1 $f17, (4 * 36 + 8 * 17)($4)
ldc1 $f18, (4 * 36 + 8 * 18)($4)
ldc1 $f19, (4 * 36 + 8 * 19)($4)
ldc1 $f20, (4 * 36 + 8 * 20)($4)
ldc1 $f21, (4 * 36 + 8 * 21)($4)
ldc1 $f22, (4 * 36 + 8 * 22)($4)
ldc1 $f23, (4 * 36 + 8 * 23)($4)
ldc1 $f24, (4 * 36 + 8 * 24)($4)
ldc1 $f25, (4 * 36 + 8 * 25)($4)
ldc1 $f26, (4 * 36 + 8 * 26)($4)
ldc1 $f27, (4 * 36 + 8 * 27)($4)
ldc1 $f28, (4 * 36 + 8 * 28)($4)
ldc1 $f29, (4 * 36 + 8 * 29)($4)
ldc1 $f30, (4 * 36 + 8 * 30)($4)
ldc1 $f31, (4 * 36 + 8 * 31)($4)
#endif
#endif
// restore hi and lo // restore hi and lo
lw $8, (4 * 33)($4) lw $8, (4 * 33)($4)
mthi $8 mthi $8
@ -856,7 +908,7 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv)
lw $4, (4 * 4)($4) lw $4, (4 * 4)($4)
.set pop .set pop
#elif defined(__mips64) && defined(__mips_soft_float) #elif defined(__mips64)
// //
// void libunwind::Registers_mips_newabi::jumpto() // void libunwind::Registers_mips_newabi::jumpto()
@ -869,6 +921,40 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind21Registers_mips_newabi6jumptoEv)
.set noat .set noat
.set noreorder .set noreorder
.set nomacro .set nomacro
#ifdef __mips_hard_float
ldc1 $f0, (8 * 35)($4)
ldc1 $f1, (8 * 36)($4)
ldc1 $f2, (8 * 37)($4)
ldc1 $f3, (8 * 38)($4)
ldc1 $f4, (8 * 39)($4)
ldc1 $f5, (8 * 40)($4)
ldc1 $f6, (8 * 41)($4)
ldc1 $f7, (8 * 42)($4)
ldc1 $f8, (8 * 43)($4)
ldc1 $f9, (8 * 44)($4)
ldc1 $f10, (8 * 45)($4)
ldc1 $f11, (8 * 46)($4)
ldc1 $f12, (8 * 47)($4)
ldc1 $f13, (8 * 48)($4)
ldc1 $f14, (8 * 49)($4)
ldc1 $f15, (8 * 50)($4)
ldc1 $f16, (8 * 51)($4)
ldc1 $f17, (8 * 52)($4)
ldc1 $f18, (8 * 53)($4)
ldc1 $f19, (8 * 54)($4)
ldc1 $f20, (8 * 55)($4)
ldc1 $f21, (8 * 56)($4)
ldc1 $f22, (8 * 57)($4)
ldc1 $f23, (8 * 58)($4)
ldc1 $f24, (8 * 59)($4)
ldc1 $f25, (8 * 60)($4)
ldc1 $f26, (8 * 61)($4)
ldc1 $f27, (8 * 62)($4)
ldc1 $f28, (8 * 63)($4)
ldc1 $f29, (8 * 64)($4)
ldc1 $f30, (8 * 65)($4)
ldc1 $f31, (8 * 66)($4)
#endif
// restore hi and lo // restore hi and lo
ld $8, (8 * 33)($4) ld $8, (8 * 33)($4)
mthi $8 mthi $8

92
libunwind/src/UnwindRegistersSave.S
View File

@ -116,8 +116,7 @@ DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
xorl %eax, %eax # return UNW_ESUCCESS xorl %eax, %eax # return UNW_ESUCCESS
ret ret
#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32 && \ #elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32
defined(__mips_soft_float)
# #
# extern int unw_getcontext(unw_context_t* thread_state) # extern int unw_getcontext(unw_context_t* thread_state)
@ -168,12 +167,65 @@ DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
sw $8, (4 * 33)($4) sw $8, (4 * 33)($4)
mflo $8 mflo $8
sw $8, (4 * 34)($4) sw $8, (4 * 34)($4)
#ifdef __mips_hard_float
#if __mips_fpr == 32
sdc1 $f0, (4 * 36 + 8 * 0)($4)
sdc1 $f2, (4 * 36 + 8 * 2)($4)
sdc1 $f4, (4 * 36 + 8 * 4)($4)
sdc1 $f6, (4 * 36 + 8 * 6)($4)
sdc1 $f8, (4 * 36 + 8 * 8)($4)
sdc1 $f10, (4 * 36 + 8 * 10)($4)
sdc1 $f12, (4 * 36 + 8 * 12)($4)
sdc1 $f14, (4 * 36 + 8 * 14)($4)
sdc1 $f16, (4 * 36 + 8 * 16)($4)
sdc1 $f18, (4 * 36 + 8 * 18)($4)
sdc1 $f20, (4 * 36 + 8 * 20)($4)
sdc1 $f22, (4 * 36 + 8 * 22)($4)
sdc1 $f24, (4 * 36 + 8 * 24)($4)
sdc1 $f26, (4 * 36 + 8 * 26)($4)
sdc1 $f28, (4 * 36 + 8 * 28)($4)
sdc1 $f30, (4 * 36 + 8 * 30)($4)
#else
sdc1 $f0, (4 * 36 + 8 * 0)($4)
sdc1 $f1, (4 * 36 + 8 * 1)($4)
sdc1 $f2, (4 * 36 + 8 * 2)($4)
sdc1 $f3, (4 * 36 + 8 * 3)($4)
sdc1 $f4, (4 * 36 + 8 * 4)($4)
sdc1 $f5, (4 * 36 + 8 * 5)($4)
sdc1 $f6, (4 * 36 + 8 * 6)($4)
sdc1 $f7, (4 * 36 + 8 * 7)($4)
sdc1 $f8, (4 * 36 + 8 * 8)($4)
sdc1 $f9, (4 * 36 + 8 * 9)($4)
sdc1 $f10, (4 * 36 + 8 * 10)($4)
sdc1 $f11, (4 * 36 + 8 * 11)($4)
sdc1 $f12, (4 * 36 + 8 * 12)($4)
sdc1 $f13, (4 * 36 + 8 * 13)($4)
sdc1 $f14, (4 * 36 + 8 * 14)($4)
sdc1 $f15, (4 * 36 + 8 * 15)($4)
sdc1 $f16, (4 * 36 + 8 * 16)($4)
sdc1 $f17, (4 * 36 + 8 * 17)($4)
sdc1 $f18, (4 * 36 + 8 * 18)($4)
sdc1 $f19, (4 * 36 + 8 * 19)($4)
sdc1 $f20, (4 * 36 + 8 * 20)($4)
sdc1 $f21, (4 * 36 + 8 * 21)($4)
sdc1 $f22, (4 * 36 + 8 * 22)($4)
sdc1 $f23, (4 * 36 + 8 * 23)($4)
sdc1 $f24, (4 * 36 + 8 * 24)($4)
sdc1 $f25, (4 * 36 + 8 * 25)($4)
sdc1 $f26, (4 * 36 + 8 * 26)($4)
sdc1 $f27, (4 * 36 + 8 * 27)($4)
sdc1 $f28, (4 * 36 + 8 * 28)($4)
sdc1 $f29, (4 * 36 + 8 * 29)($4)
sdc1 $f30, (4 * 36 + 8 * 30)($4)
sdc1 $f31, (4 * 36 + 8 * 31)($4)
#endif
#endif
jr $31 jr $31
# return UNW_ESUCCESS # return UNW_ESUCCESS
or $2, $0, $0 or $2, $0, $0
.set pop .set pop
#elif defined(__mips64) && defined(__mips_soft_float) #elif defined(__mips64)
# #
# extern int unw_getcontext(unw_context_t* thread_state) # extern int unw_getcontext(unw_context_t* thread_state)
@ -224,6 +276,40 @@ DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
sd $8, (8 * 33)($4) sd $8, (8 * 33)($4)
mflo $8 mflo $8
sd $8, (8 * 34)($4) sd $8, (8 * 34)($4)
#ifdef __mips_hard_float
sdc1 $f0, (8 * 35)($4)
sdc1 $f1, (8 * 36)($4)
sdc1 $f2, (8 * 37)($4)
sdc1 $f3, (8 * 38)($4)
sdc1 $f4, (8 * 39)($4)
sdc1 $f5, (8 * 40)($4)
sdc1 $f6, (8 * 41)($4)
sdc1 $f7, (8 * 42)($4)
sdc1 $f8, (8 * 43)($4)
sdc1 $f9, (8 * 44)($4)
sdc1 $f10, (8 * 45)($4)
sdc1 $f11, (8 * 46)($4)
sdc1 $f12, (8 * 47)($4)
sdc1 $f13, (8 * 48)($4)
sdc1 $f14, (8 * 49)($4)
sdc1 $f15, (8 * 50)($4)
sdc1 $f16, (8 * 51)($4)
sdc1 $f17, (8 * 52)($4)
sdc1 $f18, (8 * 53)($4)
sdc1 $f19, (8 * 54)($4)
sdc1 $f20, (8 * 55)($4)
sdc1 $f21, (8 * 56)($4)
sdc1 $f22, (8 * 57)($4)
sdc1 $f23, (8 * 58)($4)
sdc1 $f24, (8 * 59)($4)
sdc1 $f25, (8 * 60)($4)
sdc1 $f26, (8 * 61)($4)
sdc1 $f27, (8 * 62)($4)
sdc1 $f28, (8 * 63)($4)
sdc1 $f29, (8 * 64)($4)
sdc1 $f30, (8 * 65)($4)
sdc1 $f31, (8 * 66)($4)
#endif
jr $31 jr $31
# return UNW_ESUCCESS # return UNW_ESUCCESS
or $2, $0, $0 or $2, $0, $0

5
libunwind/src/libunwind.cpp
View File

@ -61,10 +61,9 @@ _LIBUNWIND_EXPORT int unw_init_local(unw_cursor_t *cursor,
# define REGISTER_KIND Registers_arm # define REGISTER_KIND Registers_arm
#elif defined(__or1k__) #elif defined(__or1k__)
# define REGISTER_KIND Registers_or1k # define REGISTER_KIND Registers_or1k
#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32 && \ #elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32
defined(__mips_soft_float)
# define REGISTER_KIND Registers_mips_o32 # define REGISTER_KIND Registers_mips_o32
#elif defined(__mips64) && defined(__mips_soft_float) #elif defined(__mips64)
# define REGISTER_KIND Registers_mips_newabi # define REGISTER_KIND Registers_mips_newabi
#elif defined(__mips__) #elif defined(__mips__)
# warning The MIPS architecture is not supported with this ABI and environment! # warning The MIPS architecture is not supported with this ABI and environment!