mirror of
https://github.com/capstone-engine/llvm-capstone.git
synced 2024-11-24 06:10:12 +00:00
[RISC-V] Zvk update to 0.9.7, Zvknc/Zvksc
Update the RISC-V Zvk (vector cryptography) extension support from 0.5
to version 0.9.7 (2023-05-31), per
<https://github.com/riscv/riscv-crypto/releases/download/v20230531/riscv-crypto-spec-vector.pdf>
Differences:
- Zvbc is dropped from Zvkn and Zvks, and by extension
from Zvkng and Zvksg;
- new combo extensions Zvknc and Zvksc are introduced,
adding Zvbc to Zvkn and Zvks;
- the experimentatl extensions are tagged as "0.9",
from the earlier "0.5".
Reviewed By: 4vtomat
Differential Revision: https://reviews.llvm.org/D152117
This commit is contained in:
Eric Gouriou
Craig Topper
parent
eae59aef6f
commit
c5a88fe3d0
@ -55,11 +55,13 @@
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// CHECK-NOT: __riscv_zvbc {{.*$}}
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// CHECK-NOT: __riscv_zvkg {{.*$}}
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// CHECK-NOT: __riscv_zvkn {{.*$}}
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// CHECK-NOT: __riscv_zvknc {{.*$}}
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// CHECK-NOT: __riscv_zvkned {{.*$}}
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// CHECK-NOT: __riscv_zvkng {{.*$}}
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// CHECK-NOT: __riscv_zvknha {{.*$}}
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// CHECK-NOT: __riscv_zvknhb {{.*$}}
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// CHECK-NOT: __riscv_zvks {{.*$}}
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// CHECK-NOT: __riscv_zvksc {{.*$}}
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// CHECK-NOT: __riscv_zvksed {{.*$}}
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// CHECK-NOT: __riscv_zvksg {{.*$}}
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// CHECK-NOT: __riscv_zvksh {{.*$}}
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@ -551,108 +553,124 @@
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// CHECK-ZFA-EXT: __riscv_zfa 2000{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zve64x_zvbb0p5 -x c -E -dM %s \
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// RUN: -march=rv32i_zve64x_zvbb0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBB-EXT %s
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// RUN: %clang -target riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zve64x_zvbb0p5 -x c -E -dM %s \
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// RUN: -march=rv64i_zve64x_zvbb0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBB-EXT %s
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// CHECK-ZVBB-EXT: __riscv_zvbb 5000{{$}}
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// CHECK-ZVBB-EXT: __riscv_zvbb 9000{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zve64x_zvbc0p5 -x c -E -dM %s \
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// RUN: -march=rv32i_zve64x_zvbc0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBC-EXT %s
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// RUN: %clang -target riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zve64x_zvbc0p5 -x c -E -dM %s \
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// RUN: -march=rv64i_zve64x_zvbc0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBC-EXT %s
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// CHECK-ZVBC-EXT: __riscv_zvbc 5000{{$}}
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// CHECK-ZVBC-EXT: __riscv_zvbc 9000{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zve32x_zvkg0p5 -x c -E -dM %s \
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// RUN: -march=rv32i_zve32x_zvkg0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s
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// RUN: %clang -target riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zve32x_zvkg0p5 -x c -E -dM %s \
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// RUN: -march=rv64i_zve32x_zvkg0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s
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// CHECK-ZVKG-EXT: __riscv_zvkg 5000{{$}}
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// CHECK-ZVKG-EXT: __riscv_zvkg 9000{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zve64x_zvkn0p5 -x c -E -dM %s \
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// RUN: -march=rv32i_zve64x_zvkn0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKN-EXT %s
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// RUN: %clang -target riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zve64x_zvkn0p5 -x c -E -dM %s \
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// RUN: -march=rv64i_zve64x_zvkn0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKN-EXT %s
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// CHECK-ZVKN-EXT: __riscv_zvkn 5000{{$}}
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// CHECK-ZVKN-EXT: __riscv_zvkn 9000{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zve64x_zvkng0p5 -x c -E -dM %s \
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// RUN: -march=rv32i_zve64x_zvknc0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNC-EXT %s
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// RUN: %clang -target riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zve64x_zvknc0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNC-EXT %s
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// CHECK-ZVKNC-EXT: __riscv_zvknc 9000{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zve64x_zvkng0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNG-EXT %s
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// RUN: %clang -target riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zve64x_zvkng0p5 -x c -E -dM %s \
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// RUN: -march=rv64i_zve64x_zvkng0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNG-EXT %s
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// CHECK-ZVKNG-EXT: __riscv_zvkng 5000{{$}}
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// CHECK-ZVKNG-EXT: __riscv_zvkng 9000{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zve32x_zvknha0p5 -x c -E -dM %s \
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// RUN: -march=rv32i_zve32x_zvknha0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s
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// RUN: %clang -target riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zve32x_zvknha0p5 -x c -E -dM %s \
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// RUN: -march=rv64i_zve32x_zvknha0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s
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// CHECK-ZVKNHA-EXT: __riscv_zvknha 5000{{$}}
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// CHECK-ZVKNHA-EXT: __riscv_zvknha 9000{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zve64x_zvknhb0p5 -x c -E -dM %s \
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// RUN: -march=rv32i_zve64x_zvknhb0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s
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// RUN: %clang -target riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zve64x_zvknhb0p5 -x c -E -dM %s \
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// RUN: -march=rv64i_zve64x_zvknhb0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s
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// CHECK-ZVKNHB-EXT: __riscv_zvknhb 5000{{$}}
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// CHECK-ZVKNHB-EXT: __riscv_zvknhb 9000{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zve32x_zvkned0p5 -x c -E -dM %s \
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// RUN: -march=rv32i_zve32x_zvkned0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNED-EXT %s
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// RUN: %clang -target riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zve32x_zvkned0p5 -x c -E -dM %s \
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// RUN: -march=rv64i_zve32x_zvkned0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNED-EXT %s
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// CHECK-ZVKNED-EXT: __riscv_zvkned 5000{{$}}
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// CHECK-ZVKNED-EXT: __riscv_zvkned 9000{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zve64x_zvks0p5 -x c -E -dM %s \
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// RUN: -march=rv32i_zve64x_zvks0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKS-EXT %s
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// RUN: %clang -target riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zve64x_zvks0p5 -x c -E -dM %s \
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// RUN: -march=rv64i_zve64x_zvks0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKS-EXT %s
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// CHECK-ZVKS-EXT: __riscv_zvks 5000{{$}}
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// CHECK-ZVKS-EXT: __riscv_zvks 9000{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zve32x_zvksed0p5 -x c -E -dM %s \
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// RUN: -march=rv32i_zve64x_zvksc0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSC-EXT %s
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// RUN: %clang -target riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zve64x_zvksc0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSC-EXT %s
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// CHECK-ZVKSC-EXT: __riscv_zvksc 9000{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zve32x_zvksed0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s
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// RUN: %clang -target riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zve32x_zvksed0p5 -x c -E -dM %s \
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// RUN: -march=rv64i_zve32x_zvksed0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s
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// CHECK-ZVKSED-EXT: __riscv_zvksed 5000{{$}}
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// CHECK-ZVKSED-EXT: __riscv_zvksed 9000{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zve64x_zvksg0p5 -x c -E -dM %s \
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// RUN: -march=rv32i_zve64x_zvksg0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSG-EXT %s
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// RUN: %clang -target riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zve64x_zvksg0p5 -x c -E -dM %s \
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// RUN: -march=rv64i_zve64x_zvksg0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSG-EXT %s
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// CHECK-ZVKSG-EXT: __riscv_zvksg 5000{{$}}
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// CHECK-ZVKSG-EXT: __riscv_zvksg 9000{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zve32x_zvksh0p5 -x c -E -dM %s \
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// RUN: -march=rv32i_zve32x_zvksh0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s
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// RUN: %clang -target riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zve32x_zvksh0p5 -x c -E -dM %s \
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// RUN: -march=rv64i_zve32x_zvksh0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s
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// CHECK-ZVKSH-EXT: __riscv_zvksh 5000{{$}}
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// CHECK-ZVKSH-EXT: __riscv_zvksh 9000{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zve32x_zvkt0p5 -x c -E -dM %s \
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// RUN: -march=rv32i_zve32x_zvkt0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
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// RUN: %clang -target riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zve32x_zvkt0p5 -x c -E -dM %s \
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// RUN: -march=rv64i_zve32x_zvkt0p9 -x c -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s
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// CHECK-ZVKT-EXT: __riscv_zvkt 5000{{$}}
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// CHECK-ZVKT-EXT: __riscv_zvkt 9000{{$}}
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// RUN: %clang -target riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \
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@ -225,8 +225,8 @@ The primary goal of experimental support is to assist in the process of ratifica
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``experimental-zvfh``
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LLVM implements `this draft text <https://github.com/riscv/riscv-v-spec/pull/780>`__.
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``experimental-zvbb``, ``experimental-zvbc``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvkng``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvkns``, ``experimental-zvks``, ``experimental-zvksed``, ``experimental-zvksg``, ``experimental-zvksh``, ``experimental-zvkt``
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LLVM implements the `0.5 draft specification <https://github.com/riscv/riscv-crypto/releases/download/v20230407/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
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``experimental-zvbb``, ``experimental-zvbc``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknc``, ``experimental-zvkned``, ``experimental-zvkng``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvks``, ``experimental-zvksc``, ``experimental-zvksed``, ``experimental-zvksg``, ``experimental-zvksh``, ``experimental-zvkt``
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LLVM implements the `0.9.7 draft specification <https://github.com/riscv/riscv-crypto/releases/download/v20230531/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
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To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
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@ -155,19 +155,21 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
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{"ztso", RISCVExtensionVersion{0, 1}},
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// vector crypto
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{"zvbb", RISCVExtensionVersion{0, 5}},
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{"zvbc", RISCVExtensionVersion{0, 5}},
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{"zvkg", RISCVExtensionVersion{0, 5}},
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{"zvkn", RISCVExtensionVersion{0, 5}},
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{"zvkned", RISCVExtensionVersion{0, 5}},
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{"zvkng", RISCVExtensionVersion{0, 5}},
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{"zvknha", RISCVExtensionVersion{0, 5}},
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{"zvknhb", RISCVExtensionVersion{0, 5}},
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{"zvks", RISCVExtensionVersion{0, 5}},
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{"zvksed", RISCVExtensionVersion{0, 5}},
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{"zvksg", RISCVExtensionVersion{0, 5}},
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{"zvksh", RISCVExtensionVersion{0, 5}},
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{"zvkt", RISCVExtensionVersion{0, 5}},
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{"zvbb", RISCVExtensionVersion{0, 9}},
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{"zvbc", RISCVExtensionVersion{0, 9}},
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{"zvkg", RISCVExtensionVersion{0, 9}},
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{"zvkn", RISCVExtensionVersion{0, 9}},
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{"zvknc", RISCVExtensionVersion{0, 9}},
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{"zvkned", RISCVExtensionVersion{0, 9}},
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{"zvkng", RISCVExtensionVersion{0, 9}},
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{"zvknha", RISCVExtensionVersion{0, 9}},
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{"zvknhb", RISCVExtensionVersion{0, 9}},
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{"zvks", RISCVExtensionVersion{0, 9}},
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{"zvksc", RISCVExtensionVersion{0, 9}},
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{"zvksed", RISCVExtensionVersion{0, 9}},
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{"zvksg", RISCVExtensionVersion{0, 9}},
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{"zvksh", RISCVExtensionVersion{0, 9}},
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{"zvkt", RISCVExtensionVersion{0, 9}},
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};
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static bool stripExperimentalPrefix(StringRef &Ext) {
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@ -944,13 +946,13 @@ static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
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static const char *ImpliedExtsZvfbfmin[] = {"zve32f"};
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static const char *ImpliedExtsZvfbfwma[] = {"zve32f"};
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static const char *ImpliedExtsZvfh[] = {"zve32f", "zfhmin"};
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static const char *ImpliedExtsZvkn[] = {"zvbb", "zvbc", "zvkned", "zvknhb",
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"zvkt"};
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static const char *ImpliedExtsZvkn[] = {"zvbb", "zvkned", "zvknhb", "zvkt"};
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static const char *ImpliedExtsZvknc[] = {"zvbc", "zvkn"};
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static const char *ImpliedExtsZvkng[] = {"zvkg", "zvkn"};
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static const char *ImpliedExtsZvknhb[] = {"zvknha"};
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static const char *ImpliedExtsZvks[] = {"zvbb", "zvbc", "zvksed", "zvksh",
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"zvkt"};
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static const char *ImpliedExtsZvksg[] = {"zvks", "zvkg"};
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static const char *ImpliedExtsZvks[] = {"zvbb", "zvksed", "zvksh", "zvkt"};
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static const char *ImpliedExtsZvksc[] = {"zvbc", "zvks"};
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static const char *ImpliedExtsZvksg[] = {"zvkg", "zvks"};
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static const char *ImpliedExtsZvl1024b[] = {"zvl512b"};
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static const char *ImpliedExtsZvl128b[] = {"zvl64b"};
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static const char *ImpliedExtsZvl16384b[] = {"zvl8192b"};
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@ -1006,9 +1008,11 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = {
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{{"zvfbfwma"}, {ImpliedExtsZvfbfwma}},
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{{"zvfh"}, {ImpliedExtsZvfh}},
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||||
{{"zvkn"}, {ImpliedExtsZvkn}},
|
||||
{{"zvknc"}, {ImpliedExtsZvknc}},
|
||||
{{"zvkng"}, {ImpliedExtsZvkng}},
|
||||
{{"zvknhb"}, {ImpliedExtsZvknhb}},
|
||||
{{"zvks"}, {ImpliedExtsZvks}},
|
||||
{{"zvksc"}, {ImpliedExtsZvksc}},
|
||||
{{"zvksg"}, {ImpliedExtsZvksg}},
|
||||
{{"zvl1024b"}, {ImpliedExtsZvl1024b}},
|
||||
{{"zvl128b"}, {ImpliedExtsZvl128b}},
|
||||
|
||||
@ -555,6 +555,11 @@ def FeatureStdExtZvkn
|
||||
"This extension is shorthand for the following set of "
|
||||
"other extensions: Zvkned, Zvknhb, Zvbb, Zvbc, and Zvkt.">;
|
||||
|
||||
def FeatureStdExtZvknc
|
||||
: SubtargetFeature<"experimental-zvknc", "HasStdExtZvknc", "true",
|
||||
"This extension is shorthand for the following set of "
|
||||
"other extensions: Zvkn and Zvbc.">;
|
||||
|
||||
def FeatureStdExtZvkned
|
||||
: SubtargetFeature<"experimental-zvkned", "HasStdExtZvkned", "true",
|
||||
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
|
||||
@ -584,6 +589,11 @@ def FeatureStdExtZvks
|
||||
"This extension is shorthand for the following set of "
|
||||
"other extensions: Zvksed, Zvksh, Zvbb, Zvbc, and Zvkt.">;
|
||||
|
||||
def FeatureStdExtZvksc
|
||||
: SubtargetFeature<"experimental-zvksc", "HasStdExtZvksc", "true",
|
||||
"This extension is shorthand for the following set of "
|
||||
"other extensions: Zvks and Zvbc.">;
|
||||
|
||||
def FeatureStdExtZvksed
|
||||
: SubtargetFeature<"experimental-zvksed", "HasStdExtZvksed", "true",
|
||||
"'Zvksed' (SM4 Block Cipher Instructions)">;
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file describes the RISC-V instructions from the standard 'Zvk',
|
||||
// Vector Cryptography Instructions extension, version 0.5.1.
|
||||
// Vector Cryptography Instructions extension, version 0.9.7.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
|
||||
@ -62,11 +62,13 @@
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV32ZVBC %s
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV32ZVKG %s
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV32ZVKN %s
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvknc %s -o - | FileCheck --check-prefix=RV32ZVKNC %s
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV32ZVKNED %s
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkng %s -o - | FileCheck --check-prefix=RV32ZVKNG %s
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV32ZVKNHA %s
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV32ZVKNHB %s
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV32ZVKS %s
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvksc %s -o - | FileCheck --check-prefix=RV32ZVKSC %s
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvksg %s -o - | FileCheck --check-prefix=RV32ZVKSG %s
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
|
||||
@ -146,13 +148,15 @@
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvbc %s -o - | FileCheck --check-prefix=RV64ZVBC %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV64ZVKG %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV64ZVKN %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvknc %s -o - | FileCheck --check-prefix=RV64ZVKNC %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV64ZVKNED %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkng %s -o - | FileCheck --check-prefix=RV64ZVKNG %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV64ZVKNHA %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV64ZVKNHB %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV64ZVKS %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV64ZVKS %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvksc %s -o - | FileCheck --check-prefix=RV64ZVKSC %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV64ZVKSED %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvksg %s -o - | FileCheck --check-prefix=RV64ZVKSG %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksg %s -o - | FileCheck --check-prefix=RV64ZVKSG %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
|
||||
@ -221,19 +225,21 @@
|
||||
; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr1p0_zicsr2p0"
|
||||
; RV32ZIHPM: .attribute 5, "rv32i2p1_zicsr2p0_zihpm1p0"
|
||||
; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2"
|
||||
; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zve32x1p0_zvl32b1p0"
|
||||
; RV32ZVBC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc0p5_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
|
||||
; RV32ZVKG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p5_zvl32b1p0"
|
||||
; RV32ZVKN: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkn0p5_zvkned0p5_zvknha0p5_zvknhb0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
|
||||
; RV32ZVKNED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p5_zvl32b1p0"
|
||||
; RV32ZVKNG: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkg0p5_zvkn0p5_zvkned0p5_zvkng0p5_zvknha0p5_zvknhb0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
|
||||
; RV32ZVKNHA: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p5_zvl32b1p0"
|
||||
; RV32ZVKNHB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p5_zvknhb0p5_zvl32b1p0_zvl64b1p0"
|
||||
; RV32ZVKS: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvks0p5_zvksed0p5_zvksh0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
|
||||
; RV32ZVKSED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p5_zvl32b1p0"
|
||||
; RV32ZVKSG: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkg0p5_zvks0p5_zvksed0p5_zvksg0p5_zvksh0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
|
||||
; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p5_zvl32b1p0"
|
||||
; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt0p5_zvl32b1p0"
|
||||
; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zvl32b1p0"
|
||||
; RV32ZVBC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc0p9_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
|
||||
; RV32ZVKG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p9_zvl32b1p0"
|
||||
; RV32ZVKN: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
|
||||
; RV32ZVKNC: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvknc0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
|
||||
; RV32ZVKNED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p9_zvl32b1p0"
|
||||
; RV32ZVKNG: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvkn0p9_zvkned0p9_zvkng0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
|
||||
; RV32ZVKNHA: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p9_zvl32b1p0"
|
||||
; RV32ZVKNHB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p9_zvknhb0p9_zvl32b1p0_zvl64b1p0"
|
||||
; RV32ZVKS: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
|
||||
; RV32ZVKSC: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksc0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
|
||||
; RV32ZVKSED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p9_zvl32b1p0"
|
||||
; RV32ZVKSG: .attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvks0p9_zvksed0p9_zvksg0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
|
||||
; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p9_zvl32b1p0"
|
||||
; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt0p9_zvl32b1p0"
|
||||
; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
|
||||
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
|
||||
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
|
||||
@ -304,19 +310,21 @@
|
||||
; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr1p0_zicsr2p0"
|
||||
; RV64ZIHPM: .attribute 5, "rv64i2p1_zicsr2p0_zihpm1p0"
|
||||
; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p2"
|
||||
; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p5_zve32x1p0_zvl32b1p0"
|
||||
; RV64ZVBC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc0p5_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
|
||||
; RV64ZVKG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg0p5_zvl32b1p0"
|
||||
; RV64ZVKN: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkn0p5_zvkned0p5_zvknha0p5_zvknhb0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
|
||||
; RV64ZVKNED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkned0p5_zvl32b1p0"
|
||||
; RV64ZVKNG: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkg0p5_zvkn0p5_zvkned0p5_zvkng0p5_zvknha0p5_zvknhb0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
|
||||
; RV64ZVKNHA: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvknha0p5_zvl32b1p0"
|
||||
; RV64ZVKNHB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p5_zvknhb0p5_zvl32b1p0_zvl64b1p0"
|
||||
; RV64ZVKS: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvks0p5_zvksed0p5_zvksh0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
|
||||
; RV64ZVKSED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksed0p5_zvl32b1p0"
|
||||
; RV64ZVKSG: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkg0p5_zvks0p5_zvksed0p5_zvksg0p5_zvksh0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
|
||||
; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh0p5_zvl32b1p0"
|
||||
; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt0p5_zvl32b1p0"
|
||||
; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zvl32b1p0"
|
||||
; RV64ZVBC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc0p9_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
|
||||
; RV64ZVKG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg0p9_zvl32b1p0"
|
||||
; RV64ZVKN: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
|
||||
; RV64ZVKNC: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvknc0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
|
||||
; RV64ZVKNED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkned0p9_zvl32b1p0"
|
||||
; RV64ZVKNG: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvkn0p9_zvkned0p9_zvkng0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
|
||||
; RV64ZVKNHA: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvknha0p9_zvl32b1p0"
|
||||
; RV64ZVKNHB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p9_zvknhb0p9_zvl32b1p0_zvl64b1p0"
|
||||
; RV64ZVKS: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zvks0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0"
|
||||
; RV64ZVKSC: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksc0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
|
||||
; RV64ZVKSED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksed0p9_zvl32b1p0"
|
||||
; RV64ZVKSG: .attribute 5, "rv64i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zvkg0p9_zvks0p9_zvksed0p9_zvksg0p9_zvksh0p9_zvkt0p9_zvl32b1p0"
|
||||
; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh0p9_zvl32b1p0"
|
||||
; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt0p9_zvl32b1p0"
|
||||
; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0"
|
||||
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
|
||||
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
|
||||
|
||||
@ -111,44 +111,50 @@
|
||||
.attribute arch, "rv32izbc1p0"
|
||||
# CHECK: attribute 5, "rv32i2p1_zbc1p0"
|
||||
|
||||
.attribute arch, "rv32i_zve64x_zvbb0p5"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
|
||||
.attribute arch, "rv32i_zve64x_zvbb0p9"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
|
||||
|
||||
.attribute arch, "rv32i_zve64x_zvbc0p5"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbc0p5_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
|
||||
.attribute arch, "rv32i_zve64x_zvbc0p9"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbc0p9_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
|
||||
|
||||
.attribute arch, "rv32i_zve32x_zvkg0p5"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p5_zvl32b1p0"
|
||||
.attribute arch, "rv32i_zve32x_zvkg0p9"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p9_zvl32b1p0"
|
||||
|
||||
.attribute arch, "rv32i_zve64x_zvkn0p5"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkn0p5_zvkned0p5_zvknha0p5_zvknhb0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
|
||||
.attribute arch, "rv32i_zve64x_zvkn0p9"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
|
||||
|
||||
.attribute arch, "rv32i_zve64x_zvknc0p9"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvknc0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
|
||||
|
||||
.attribute arch, "rv32i_zve64x_zvkng0p5"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkg0p5_zvkn0p5_zvkned0p5_zvkng0p5_zvknha0p5_zvknhb0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
|
||||
.attribute arch, "rv32i_zve64x_zvkng0p9"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvkn0p9_zvkned0p9_zvkng0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
|
||||
|
||||
.attribute arch, "rv32i_zve32x_zvknha0p5"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p5_zvl32b1p0"
|
||||
.attribute arch, "rv32i_zve32x_zvknha0p9"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p9_zvl32b1p0"
|
||||
|
||||
.attribute arch, "rv32i_zve64x_zvknhb0p5"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p5_zvknhb0p5_zvl32b1p0_zvl64b1p0"
|
||||
.attribute arch, "rv32i_zve64x_zvknhb0p9"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p9_zvknhb0p9_zvl32b1p0_zvl64b1p0"
|
||||
|
||||
.attribute arch, "rv32i_zve32x_zvkned0p5"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p5_zvl32b1p0"
|
||||
.attribute arch, "rv32i_zve32x_zvkned0p9"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p9_zvl32b1p0"
|
||||
|
||||
.attribute arch, "rv32i_zve64x_zvks0p5"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvks0p5_zvksed0p5_zvksh0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
|
||||
.attribute arch, "rv32i_zve64x_zvks0p9"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
|
||||
|
||||
.attribute arch, "rv32i_zve64x_zvksg0p5"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p5_zvbc0p5_zve32x1p0_zve64x1p0_zvkg0p5_zvks0p5_zvksed0p5_zvksg0p5_zvksh0p5_zvkt0p5_zvl32b1p0_zvl64b1p0"
|
||||
.attribute arch, "rv32i_zve64x_zvksc0p9"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksc0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
|
||||
|
||||
.attribute arch, "rv32i_zve32x_zvksed0p5"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p5_zvl32b1p0"
|
||||
.attribute arch, "rv32i_zve64x_zvksg0p9"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvks0p9_zvksed0p9_zvksg0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
|
||||
|
||||
.attribute arch, "rv32i_zve32x_zvksh0p5"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p5_zvl32b1p0"
|
||||
.attribute arch, "rv32i_zve32x_zvksed0p9"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p9_zvl32b1p0"
|
||||
|
||||
.attribute arch, "rv32i_zvkt0p5"
|
||||
# CHECK: attribute 5, "rv32i2p1_zvkt0p5"
|
||||
.attribute arch, "rv32i_zve32x_zvksh0p9"
|
||||
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p9_zvl32b1p0"
|
||||
|
||||
.attribute arch, "rv32i_zvkt0p9"
|
||||
# CHECK: attribute 5, "rv32i2p1_zvkt0p9"
|
||||
|
||||
.attribute arch, "rv32izbs1p0"
|
||||
# CHECK: attribute 5, "rv32i2p1_zbs1p0"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user