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[PowerPC] Fix PR17155 - Ignore COPY_TO_REGCLASS during emit.
Fast-isel generates a COPY_TO_REGCLASS for widening f32 to f64, which is a nop on PPC64. This is needed to keep the register class system happy, but on the fast-isel path it is not removed before emit as it is for DAG select. Ignore this op when emitting instructions. llvm-svn: 190795
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@ -23,6 +23,7 @@
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetOpcodes.h"
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using namespace llvm;
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using namespace llvm;
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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@ -76,11 +77,17 @@ public:
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SmallVectorImpl<MCFixup> &Fixups) const;
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SmallVectorImpl<MCFixup> &Fixups) const;
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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SmallVectorImpl<MCFixup> &Fixups) const {
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// For fast-isel, a float COPY_TO_REGCLASS can survive this long.
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// It's just a nop to keep the register classes happy, so don't
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// generate anything.
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unsigned Opcode = MI.getOpcode();
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if (Opcode == TargetOpcode::COPY_TO_REGCLASS)
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return;
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uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
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uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
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// BL8_NOP etc. all have a size of 8 because of the following 'nop'.
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// BL8_NOP etc. all have a size of 8 because of the following 'nop'.
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unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value!
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unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value!
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unsigned Opcode = MI.getOpcode();
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if (Opcode == PPC::BL8_NOP || Opcode == PPC::BLA8_NOP ||
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if (Opcode == PPC::BL8_NOP || Opcode == PPC::BLA8_NOP ||
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Opcode == PPC::BL8_NOP_TLS)
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Opcode == PPC::BL8_NOP_TLS)
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Size = 8;
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Size = 8;
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