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[Codegen] Remove dead flags on Physical Defs in machine cse
We may leave behind incorrect dead flags on instructions that are CSE'd. Make sure we remove the dead flags on physical registers to prevent other incorrect code motion. Differential Revision: https://reviews.llvm.org/D58115 llvm-svn: 354443
This commit is contained in:
David Green
parent
30d340839c
commit
cb5a48b060
@ -94,6 +94,7 @@ namespace {
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ScopedHashTable<MachineInstr *, unsigned, MachineInstrExpressionTrait,
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AllocatorTy>;
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using ScopeType = ScopedHTType::ScopeTy;
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using PhysDefVector = SmallVector<std::pair<unsigned, unsigned>, 2>;
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unsigned LookAheadLimit = 0;
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DenseMap<MachineBasicBlock *, ScopeType *> ScopeMap;
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@ -108,13 +109,11 @@ namespace {
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MachineBasicBlock::const_iterator E) const;
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bool hasLivePhysRegDefUses(const MachineInstr *MI,
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const MachineBasicBlock *MBB,
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SmallSet<unsigned,8> &PhysRefs,
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SmallVectorImpl<unsigned> &PhysDefs,
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bool &PhysUseDef) const;
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SmallSet<unsigned, 8> &PhysRefs,
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PhysDefVector &PhysDefs, bool &PhysUseDef) const;
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bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
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SmallSet<unsigned,8> &PhysRefs,
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SmallVectorImpl<unsigned> &PhysDefs,
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bool &NonLocal) const;
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SmallSet<unsigned, 8> &PhysRefs,
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PhysDefVector &PhysDefs, bool &NonLocal) const;
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bool isCSECandidate(MachineInstr *MI);
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bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
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MachineInstr *CSMI, MachineInstr *MI);
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@ -255,9 +254,9 @@ static bool isCallerPreservedOrConstPhysReg(unsigned Reg,
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/// instruction does not uses a physical register.
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bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
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const MachineBasicBlock *MBB,
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SmallSet<unsigned,8> &PhysRefs,
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SmallVectorImpl<unsigned> &PhysDefs,
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bool &PhysUseDef) const{
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SmallSet<unsigned, 8> &PhysRefs,
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PhysDefVector &PhysDefs,
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bool &PhysUseDef) const {
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// First, add all uses to PhysRefs.
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for (const MachineOperand &MO : MI->operands()) {
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if (!MO.isReg() || MO.isDef())
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@ -277,7 +276,8 @@ bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
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// (which currently contains only uses), set the PhysUseDef flag.
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PhysUseDef = false;
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MachineBasicBlock::const_iterator I = MI; I = std::next(I);
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for (const MachineOperand &MO : MI->operands()) {
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for (const auto &MOP : llvm::enumerate(MI->operands())) {
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const MachineOperand &MO = MOP.value();
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if (!MO.isReg() || !MO.isDef())
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continue;
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unsigned Reg = MO.getReg();
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@ -292,20 +292,21 @@ bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
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// common since this pass is run before livevariables. We can scan
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// forward a few instructions and check if it is obviously dead.
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if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end()))
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PhysDefs.push_back(Reg);
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PhysDefs.push_back(std::make_pair(MOP.index(), Reg));
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}
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// Finally, add all defs to PhysRefs as well.
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for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
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for (MCRegAliasIterator AI(PhysDefs[i], TRI, true); AI.isValid(); ++AI)
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for (MCRegAliasIterator AI(PhysDefs[i].second, TRI, true); AI.isValid();
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++AI)
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PhysRefs.insert(*AI);
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return !PhysRefs.empty();
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}
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bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
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SmallSet<unsigned,8> &PhysRefs,
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SmallVectorImpl<unsigned> &PhysDefs,
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SmallSet<unsigned, 8> &PhysRefs,
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PhysDefVector &PhysDefs,
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bool &NonLocal) const {
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// For now conservatively returns false if the common subexpression is
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// not in the same basic block as the given instruction. The only exception
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@ -319,7 +320,8 @@ bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
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return false;
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for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
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if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i]))
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if (MRI->isAllocatable(PhysDefs[i].second) ||
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MRI->isReserved(PhysDefs[i].second))
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// Avoid extending live range of physical registers if they are
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//allocatable or reserved.
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return false;
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@ -535,7 +537,7 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
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// It's also not safe if the instruction uses physical registers.
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bool CrossMBBPhysDef = false;
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SmallSet<unsigned, 8> PhysRefs;
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SmallVector<unsigned, 2> PhysDefs;
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PhysDefVector PhysDefs;
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bool PhysUseDef = false;
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if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs,
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PhysDefs, PhysUseDef)) {
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@ -634,6 +636,9 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
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// we should make sure it is not dead at CSMI.
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for (unsigned ImplicitDefToUpdate : ImplicitDefsToUpdate)
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CSMI->getOperand(ImplicitDefToUpdate).setIsDead(false);
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for (auto PhysDef : PhysDefs)
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if (!MI->getOperand(PhysDef.first).isDead())
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CSMI->getOperand(PhysDef.first).setIsDead(false);
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// Go through implicit defs of CSMI and MI, and clear the kill flags on
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// their uses in all the instructions between CSMI and MI.
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@ -662,9 +667,9 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
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// Add physical register defs now coming in from a predecessor to MBB
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// livein list.
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while (!PhysDefs.empty()) {
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unsigned LiveIn = PhysDefs.pop_back_val();
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if (!MBB->isLiveIn(LiveIn))
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MBB->addLiveIn(LiveIn);
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auto LiveIn = PhysDefs.pop_back_val();
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if (!MBB->isLiveIn(LiveIn.second))
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MBB->addLiveIn(LiveIn.second);
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}
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++NumCrossBBCSEs;
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}
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103
llvm/test/CodeGen/Thumb/machine-cse-deadreg.mir
Normal file
103
llvm/test/CodeGen/Thumb/machine-cse-deadreg.mir
Normal file
@ -0,0 +1,103 @@
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# RUN: llc -mtriple thumbv6m-arm-none-eabi -run-pass=machine-cse -verify-machineinstrs -o - %s | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv6m-arm-none-eabi"
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define i32 @funca(i64 %l1) {
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entry:
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%l2 = icmp ult i64 %l1, -177673816660004267
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%l3 = add i64 %l1, 401100203
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%rem.i = select i1 %l2, i64 %l1, i64 %l3
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%conv = trunc i64 %rem.i to i32
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ret i32 %conv
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}
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define i32 @funcb(i64 %l1) { ret i32 0 }
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...
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---
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name: funca
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tracksRegLiveness: true
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$r1', virtual-reg: '%1' }
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constants:
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- id: 0
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value: i32 401100203
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alignment: 4
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isTargetSpecific: false
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- id: 1
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value: i32 41367909
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alignment: 4
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isTargetSpecific: false
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body: |
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bb.0.entry:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $r0, $r1
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%1:tgpr = COPY $r1
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%0:tgpr = COPY $r0
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%2:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool)
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%3:tgpr, dead $cpsr = tADDrr %0, %2, 14, $noreg
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%4:tgpr = tLDRpci %const.1, 14, $noreg :: (load 4 from constant-pool)
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%5:tgpr, $cpsr = tADDrr %0, %2, 14, $noreg
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%6:tgpr, $cpsr = tADC %1, killed %4, 14, $noreg, implicit $cpsr
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tBcc %bb.2, 3, $cpsr
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bb.1.entry:
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successors: %bb.2(0x80000000)
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bb.2.entry:
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%7:tgpr = PHI %3, %bb.1, %0, %bb.0
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$r0 = COPY %7
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tBX_RET 14, $noreg, implicit $r0
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# CHECK-LABEL: name: funca
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# cpsr def must not be dead
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# CHECK: %3:tgpr, $cpsr = tADDrr %0, %2
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# CHECK-NOT: %5:tgpr, $cpsr = tADDrr %0, %2
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...
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---
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name: funcb
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tracksRegLiveness: true
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liveins:
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- { reg: '$r0', virtual-reg: '%0' }
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- { reg: '$r1', virtual-reg: '%1' }
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constants:
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- id: 0
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value: i32 401100203
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alignment: 4
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isTargetSpecific: false
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- id: 1
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value: i32 41367909
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alignment: 4
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isTargetSpecific: false
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body: |
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bb.0:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $r0, $r1
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%1:tgpr = COPY $r1
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%0:tgpr = COPY $r0
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%2:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool)
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%3:tgpr, dead $cpsr = tADDrr %0, %2, 14, $noreg
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%4:tgpr = tLDRpci %const.1, 14, $noreg :: (load 4 from constant-pool)
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%5:tgpr, dead $cpsr = tADDrr %0, %2, 14, $noreg
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%6:tgpr, $cpsr = tADDrr %1, killed %4, 14, $noreg
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tBcc %bb.2, 3, $cpsr
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bb.1:
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successors: %bb.2(0x80000000)
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bb.2:
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%7:tgpr = PHI %3, %bb.1, %0, %bb.0
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$r0 = COPY %7
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tBX_RET 14, $noreg, implicit $r0
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# CHECK-LABEL: name: funcb
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# cpsr def should be dead
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# CHECK: %3:tgpr, dead $cpsr = tADDrr %0, %2
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# CHECK-NOT: %5:tgpr, dead $cpsr = tADDrr %0, %2
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...
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