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[WebAssembly] Fix trapping behavior in fptosi/fptoui.
This adds code to protect WebAssembly's `trunc_s` family of opcodes from values outside their domain. Even though such conversions have full undefined behavior in C/C++, LLVM IR's `fptosi` and `fptoui` do not, and only return undef. This also implements the proposed non-trapping float-to-int conversion feature and uses that instead when available. llvm-svn: 319128
This commit is contained in:
Dan Gohman
parent
9e3381e8dc
commit
cdd48b8a6b
@ -61,8 +61,13 @@ void WebAssemblyMCCodeEmitter::encodeInstruction(
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uint64_t Start = OS.tell();
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uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
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assert(Binary < UINT8_MAX && "Multi-byte opcodes not supported yet");
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OS << uint8_t(Binary);
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if (Binary <= UINT8_MAX) {
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OS << uint8_t(Binary);
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} else {
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assert(Binary <= UINT16_MAX && "Several-byte opcodes not supported yet");
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OS << uint8_t(Binary >> 8)
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<< uint8_t(Binary);
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}
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// For br_table instructions, encode the size of the table. In the MCInst,
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// there's an index operand, one operand for each table entry, and the
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@ -27,6 +27,10 @@ def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "true",
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"Enable 128-bit SIMD">;
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def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
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"Enable Atomics">;
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def FeatureNontrappingFPToInt :
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SubtargetFeature<"nontrapping-fptoint",
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"HasNontrappingFPToInt", "true",
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"Enable non-trapping float-to-int conversion operators">;
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//===----------------------------------------------------------------------===//
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// Architectures.
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@ -19,6 +19,7 @@
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#include "WebAssemblyTargetMachine.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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@ -184,6 +185,134 @@ MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/,
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return Result;
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}
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// Lower an fp-to-int conversion operator from the LLVM opcode, which has an
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// undefined result on invalid/overflow, to the WebAssembly opcode, which
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// traps on invalid/overflow.
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static MachineBasicBlock *
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LowerFPToInt(
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MachineInstr &MI,
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DebugLoc DL,
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MachineBasicBlock *BB,
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const TargetInstrInfo &TII,
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bool IsUnsigned,
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bool Int64,
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bool Float64,
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unsigned LoweredOpcode
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) {
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MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
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unsigned OutReg = MI.getOperand(0).getReg();
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unsigned InReg = MI.getOperand(1).getReg();
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unsigned Abs = Float64 ? WebAssembly::ABS_F64 : WebAssembly::ABS_F32;
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unsigned FConst = Float64 ? WebAssembly::CONST_F64 : WebAssembly::CONST_F32;
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unsigned LT = Float64 ? WebAssembly::LT_F64 : WebAssembly::LT_F32;
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unsigned IConst = Int64 ? WebAssembly::CONST_I64 : WebAssembly::CONST_I32;
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int64_t Limit = Int64 ? INT64_MIN : INT32_MIN;
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int64_t Substitute = IsUnsigned ? 0 : Limit;
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double CmpVal = IsUnsigned ? -(double)Limit * 2.0 : -(double)Limit;
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auto &Context = BB->getParent()->getFunction()->getContext();
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Type *Ty = Float64 ? Type::getDoubleTy(Context) : Type::getFloatTy(Context);
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *TrueMBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *FalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *DoneMBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineFunction::iterator It = ++BB->getIterator();
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F->insert(It, FalseMBB);
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F->insert(It, TrueMBB);
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F->insert(It, DoneMBB);
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// Transfer the remainder of BB and its successor edges to DoneMBB.
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DoneMBB->splice(DoneMBB->begin(), BB,
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std::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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DoneMBB->transferSuccessorsAndUpdatePHIs(BB);
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BB->addSuccessor(TrueMBB);
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BB->addSuccessor(FalseMBB);
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TrueMBB->addSuccessor(DoneMBB);
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FalseMBB->addSuccessor(DoneMBB);
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unsigned Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
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Tmp0 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
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Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
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Tmp2 = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
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Tmp3 = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
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Tmp4 = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
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MI.eraseFromParent();
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if (IsUnsigned) {
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Tmp0 = InReg;
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} else {
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BuildMI(BB, DL, TII.get(Abs), Tmp0)
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.addReg(InReg);
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}
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BuildMI(BB, DL, TII.get(FConst), Tmp1)
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.addFPImm(cast<ConstantFP>(ConstantFP::get(Ty, CmpVal)));
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BuildMI(BB, DL, TII.get(LT), Tmp2)
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.addReg(Tmp0)
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.addReg(Tmp1);
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BuildMI(BB, DL, TII.get(WebAssembly::BR_IF))
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.addMBB(TrueMBB)
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.addReg(Tmp2);
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BuildMI(FalseMBB, DL, TII.get(IConst), Tmp3)
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.addImm(Substitute);
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BuildMI(FalseMBB, DL, TII.get(WebAssembly::BR))
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.addMBB(DoneMBB);
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BuildMI(TrueMBB, DL, TII.get(LoweredOpcode), Tmp4)
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.addReg(InReg);
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BuildMI(*DoneMBB, DoneMBB->begin(), DL, TII.get(TargetOpcode::PHI), OutReg)
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.addReg(Tmp3)
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.addMBB(FalseMBB)
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.addReg(Tmp4)
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.addMBB(TrueMBB);
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return DoneMBB;
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}
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MachineBasicBlock *
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WebAssemblyTargetLowering::EmitInstrWithCustomInserter(
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MachineInstr &MI,
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MachineBasicBlock *BB
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) const {
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const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
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DebugLoc DL = MI.getDebugLoc();
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switch (MI.getOpcode()) {
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default: llvm_unreachable("Unexpected instr type to insert");
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case WebAssembly::FP_TO_SINT_I32_F32:
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return LowerFPToInt(MI, DL, BB, TII, false, false, false,
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WebAssembly::I32_TRUNC_S_F32);
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case WebAssembly::FP_TO_UINT_I32_F32:
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return LowerFPToInt(MI, DL, BB, TII, true, false, false,
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WebAssembly::I32_TRUNC_U_F32);
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case WebAssembly::FP_TO_SINT_I64_F32:
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return LowerFPToInt(MI, DL, BB, TII, false, true, false,
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WebAssembly::I64_TRUNC_S_F32);
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case WebAssembly::FP_TO_UINT_I64_F32:
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return LowerFPToInt(MI, DL, BB, TII, true, true, false,
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WebAssembly::I64_TRUNC_U_F32);
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case WebAssembly::FP_TO_SINT_I32_F64:
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return LowerFPToInt(MI, DL, BB, TII, false, false, true,
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WebAssembly::I32_TRUNC_S_F64);
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case WebAssembly::FP_TO_UINT_I32_F64:
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return LowerFPToInt(MI, DL, BB, TII, true, false, true,
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WebAssembly::I32_TRUNC_U_F64);
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case WebAssembly::FP_TO_SINT_I64_F64:
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return LowerFPToInt(MI, DL, BB, TII, false, true, true,
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WebAssembly::I64_TRUNC_S_F64);
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case WebAssembly::FP_TO_UINT_I64_F64:
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return LowerFPToInt(MI, DL, BB, TII, true, true, true,
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WebAssembly::I64_TRUNC_U_F64);
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llvm_unreachable("Unexpected instruction to emit with custom inserter");
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}
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}
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const char *WebAssemblyTargetLowering::getTargetNodeName(
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unsigned Opcode) const {
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switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
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@ -48,6 +48,9 @@ class WebAssemblyTargetLowering final : public TargetLowering {
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const TargetLibraryInfo *LibInfo) const override;
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *MBB) const override;
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const char *getTargetNodeName(unsigned Opcode) const override;
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std::pair<unsigned, const TargetRegisterClass *> getRegForInlineAsmConstraint(
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const TargetRegisterInfo *TRI, StringRef Constraint,
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@ -53,32 +53,88 @@ def : Pat<(i64 (anyext I32:$src)), (I64_EXTEND_U_I32 I32:$src)>;
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let Defs = [ARGUMENTS] in {
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// Conversion from floating point to integer instructions which don't trap on
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// overflow or invalid.
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def I32_TRUNC_S_SAT_F32 : I<(outs I32:$dst), (ins F32:$src),
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[(set I32:$dst, (fp_to_sint F32:$src))],
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"i32.trunc_s:sat/f32\t$dst, $src", 0xfc00>,
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Requires<[HasNontrappingFPToInt]>;
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def I32_TRUNC_U_SAT_F32 : I<(outs I32:$dst), (ins F32:$src),
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[(set I32:$dst, (fp_to_uint F32:$src))],
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"i32.trunc_u:sat/f32\t$dst, $src", 0xfc01>,
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Requires<[HasNontrappingFPToInt]>;
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def I64_TRUNC_S_SAT_F32 : I<(outs I64:$dst), (ins F32:$src),
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[(set I64:$dst, (fp_to_sint F32:$src))],
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"i64.trunc_s:sat/f32\t$dst, $src", 0xfc04>,
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Requires<[HasNontrappingFPToInt]>;
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def I64_TRUNC_U_SAT_F32 : I<(outs I64:$dst), (ins F32:$src),
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[(set I64:$dst, (fp_to_uint F32:$src))],
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"i64.trunc_u:sat/f32\t$dst, $src", 0xfc05>,
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Requires<[HasNontrappingFPToInt]>;
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def I32_TRUNC_S_SAT_F64 : I<(outs I32:$dst), (ins F64:$src),
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[(set I32:$dst, (fp_to_sint F64:$src))],
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"i32.trunc_s:sat/f64\t$dst, $src", 0xfc02>,
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Requires<[HasNontrappingFPToInt]>;
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def I32_TRUNC_U_SAT_F64 : I<(outs I32:$dst), (ins F64:$src),
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[(set I32:$dst, (fp_to_uint F64:$src))],
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"i32.trunc_u:sat/f64\t$dst, $src", 0xfc03>,
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Requires<[HasNontrappingFPToInt]>;
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def I64_TRUNC_S_SAT_F64 : I<(outs I64:$dst), (ins F64:$src),
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[(set I64:$dst, (fp_to_sint F64:$src))],
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"i64.trunc_s:sat/f64\t$dst, $src", 0xfc06>,
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Requires<[HasNontrappingFPToInt]>;
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def I64_TRUNC_U_SAT_F64 : I<(outs I64:$dst), (ins F64:$src),
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[(set I64:$dst, (fp_to_uint F64:$src))],
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"i64.trunc_u:sat/f64\t$dst, $src", 0xfc07>,
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Requires<[HasNontrappingFPToInt]>;
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// Conversion from floating point to integer pseudo-instructions which don't
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// trap on overflow or invalid.
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let usesCustomInserter = 1, isCodeGenOnly = 1 in {
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def FP_TO_SINT_I32_F32 : I<(outs I32:$dst), (ins F32:$src),
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[(set I32:$dst, (fp_to_sint F32:$src))], "", 0>,
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Requires<[NotHasNontrappingFPToInt]>;
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def FP_TO_UINT_I32_F32 : I<(outs I32:$dst), (ins F32:$src),
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[(set I32:$dst, (fp_to_uint F32:$src))], "", 0>,
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Requires<[NotHasNontrappingFPToInt]>;
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def FP_TO_SINT_I64_F32 : I<(outs I64:$dst), (ins F32:$src),
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[(set I64:$dst, (fp_to_sint F32:$src))], "", 0>,
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Requires<[NotHasNontrappingFPToInt]>;
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def FP_TO_UINT_I64_F32 : I<(outs I64:$dst), (ins F32:$src),
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[(set I64:$dst, (fp_to_uint F32:$src))], "", 0>,
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Requires<[NotHasNontrappingFPToInt]>;
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def FP_TO_SINT_I32_F64 : I<(outs I32:$dst), (ins F64:$src),
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[(set I32:$dst, (fp_to_sint F64:$src))], "", 0>,
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Requires<[NotHasNontrappingFPToInt]>;
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def FP_TO_UINT_I32_F64 : I<(outs I32:$dst), (ins F64:$src),
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[(set I32:$dst, (fp_to_uint F64:$src))], "", 0>,
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Requires<[NotHasNontrappingFPToInt]>;
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def FP_TO_SINT_I64_F64 : I<(outs I64:$dst), (ins F64:$src),
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[(set I64:$dst, (fp_to_sint F64:$src))], "", 0>,
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Requires<[NotHasNontrappingFPToInt]>;
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def FP_TO_UINT_I64_F64 : I<(outs I64:$dst), (ins F64:$src),
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[(set I64:$dst, (fp_to_uint F64:$src))], "", 0>,
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Requires<[NotHasNontrappingFPToInt]>;
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} // usesCustomInserter, isCodeGenOnly = 1
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// Conversion from floating point to integer traps on overflow and invalid.
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let hasSideEffects = 1 in {
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def I32_TRUNC_S_F32 : I<(outs I32:$dst), (ins F32:$src),
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[(set I32:$dst, (fp_to_sint F32:$src))],
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"i32.trunc_s/f32\t$dst, $src", 0xa8>;
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[], "i32.trunc_s/f32\t$dst, $src", 0xa8>;
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def I32_TRUNC_U_F32 : I<(outs I32:$dst), (ins F32:$src),
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[(set I32:$dst, (fp_to_uint F32:$src))],
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"i32.trunc_u/f32\t$dst, $src", 0xa9>;
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[], "i32.trunc_u/f32\t$dst, $src", 0xa9>;
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def I64_TRUNC_S_F32 : I<(outs I64:$dst), (ins F32:$src),
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[(set I64:$dst, (fp_to_sint F32:$src))],
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"i64.trunc_s/f32\t$dst, $src", 0xae>;
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[], "i64.trunc_s/f32\t$dst, $src", 0xae>;
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def I64_TRUNC_U_F32 : I<(outs I64:$dst), (ins F32:$src),
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[(set I64:$dst, (fp_to_uint F32:$src))],
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"i64.trunc_u/f32\t$dst, $src", 0xaf>;
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[], "i64.trunc_u/f32\t$dst, $src", 0xaf>;
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def I32_TRUNC_S_F64 : I<(outs I32:$dst), (ins F64:$src),
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[(set I32:$dst, (fp_to_sint F64:$src))],
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"i32.trunc_s/f64\t$dst, $src", 0xaa>;
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[], "i32.trunc_s/f64\t$dst, $src", 0xaa>;
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def I32_TRUNC_U_F64 : I<(outs I32:$dst), (ins F64:$src),
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[(set I32:$dst, (fp_to_uint F64:$src))],
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"i32.trunc_u/f64\t$dst, $src", 0xab>;
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[], "i32.trunc_u/f64\t$dst, $src", 0xab>;
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def I64_TRUNC_S_F64 : I<(outs I64:$dst), (ins F64:$src),
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[(set I64:$dst, (fp_to_sint F64:$src))],
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"i64.trunc_s/f64\t$dst, $src", 0xb0>;
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[], "i64.trunc_s/f64\t$dst, $src", 0xb0>;
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def I64_TRUNC_U_F64 : I<(outs I64:$dst), (ins F64:$src),
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[(set I64:$dst, (fp_to_uint F64:$src))],
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"i64.trunc_u/f64\t$dst, $src", 0xb1>;
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[], "i64.trunc_u/f64\t$dst, $src", 0xb1>;
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} // hasSideEffects = 1
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def F32_CONVERT_S_I32 : I<(outs F32:$dst), (ins I32:$src),
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@ -22,6 +22,14 @@ def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">,
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AssemblerPredicate<"FeatureSIMD128", "simd128">;
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def HasAtomics : Predicate<"Subtarget->hasAtomics()">,
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AssemblerPredicate<"FeatureAtomics", "atomics">;
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def HasNontrappingFPToInt :
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Predicate<"Subtarget->hasNontrappingFPToInt()">,
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AssemblerPredicate<"FeatureNontrappingFPToInt",
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"nontrapping-fptoint">;
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def NotHasNontrappingFPToInt :
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Predicate<"!Subtarget->hasNontrappingFPToInt()">,
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AssemblerPredicate<"!FeatureNontrappingFPToInt",
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"nontrapping-fptoint">;
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//===----------------------------------------------------------------------===//
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// WebAssembly-specific DAG Node Types.
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@ -41,7 +41,8 @@ WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
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const std::string &FS,
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const TargetMachine &TM)
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: WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasSIMD128(false),
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HasAtomics(false), CPUString(CPU), TargetTriple(TT), FrameLowering(),
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HasAtomics(false), HasNontrappingFPToInt(false), CPUString(CPU),
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TargetTriple(TT), FrameLowering(),
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InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
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TLInfo(TM, *this) {}
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@ -31,6 +31,7 @@ namespace llvm {
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class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
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bool HasSIMD128;
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bool HasAtomics;
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bool HasNontrappingFPToInt;
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/// String name of used CPU.
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std::string CPUString;
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@ -76,6 +77,7 @@ public:
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bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
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bool hasSIMD128() const { return HasSIMD128; }
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bool hasAtomics() const { return HasAtomics; }
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bool hasNontrappingFPToInt() const { return HasNontrappingFPToInt; }
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/// Parses features string setting specified subtarget options. Definition of
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/// function is auto generated by tblgen.
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163
llvm/test/CodeGen/WebAssembly/conv-trap.ll
Normal file
163
llvm/test/CodeGen/WebAssembly/conv-trap.ll
Normal file
@ -0,0 +1,163 @@
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-nontrapping-fptoint | FileCheck %s
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; Test that basic conversion operations assemble as expected using
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; the trapping opcodes and explicit code to suppress the trapping.
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
|
||||
target triple = "wasm32-unknown-unknown-wasm"
|
||||
|
||||
; CHECK-LABEL: i32_trunc_s_f32:
|
||||
; CHECK-NEXT: .param f32{{$}}
|
||||
; CHECK-NEXT: .result i32{{$}}
|
||||
; CHECK-NEXT: block
|
||||
; CHECK-NEXT: f32.abs $push[[ABS:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: f32.const $push[[LIMIT:[0-9]+]]=, 0x1p31{{$}}
|
||||
; CHECK-NEXT: f32.lt $push[[LT:[0-9]+]]=, $pop[[ABS]], $pop[[LIMIT]]{{$}}
|
||||
; CHECK-NEXT: i32.eqz $push[[EQZ:[0-9]+]]=, $pop[[LT]]{{$}}
|
||||
; CHECK-NEXT: br_if 0, $pop[[EQZ]]{{$}}
|
||||
; CHECK-NEXT: i32.trunc_s/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: return $pop[[NUM]]{{$}}
|
||||
; CHECK-NEXT: BB
|
||||
; CHECK-NEXT: end_block
|
||||
; CHECK-NEXT: i32.const $push[[ALT:[0-9]+]]=, -2147483648{{$}}
|
||||
; CHECK-NEXT: return $pop[[ALT]]{{$}}
|
||||
define i32 @i32_trunc_s_f32(float %x) {
|
||||
%a = fptosi float %x to i32
|
||||
ret i32 %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: i32_trunc_u_f32:
|
||||
; CHECK-NEXT: .param f32{{$}}
|
||||
; CHECK-NEXT: .result i32{{$}}
|
||||
; CHECK-NEXT: block
|
||||
; CHECK-NEXT: f32.const $push[[LIMIT:[0-9]+]]=, 0x1p32{{$}}
|
||||
; CHECK-NEXT: f32.lt $push[[LT:[0-9]+]]=, $0, $pop[[LIMIT]]{{$}}
|
||||
; CHECK-NEXT: i32.eqz $push[[EQZ:[0-9]+]]=, $pop[[LT]]{{$}}
|
||||
; CHECK-NEXT: br_if 0, $pop[[EQZ]]{{$}}
|
||||
; CHECK-NEXT: i32.trunc_u/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: return $pop[[NUM]]{{$}}
|
||||
; CHECK-NEXT: BB
|
||||
; CHECK-NEXT: end_block
|
||||
; CHECK-NEXT: i32.const $push[[ALT:[0-9]+]]=, 0{{$}}
|
||||
; CHECK-NEXT: return $pop[[ALT]]{{$}}
|
||||
define i32 @i32_trunc_u_f32(float %x) {
|
||||
%a = fptoui float %x to i32
|
||||
ret i32 %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: i32_trunc_s_f64:
|
||||
; CHECK-NEXT: .param f64{{$}}
|
||||
; CHECK-NEXT: .result i32{{$}}
|
||||
; CHECK-NEXT: block
|
||||
; CHECK-NEXT: f64.abs $push[[ABS:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: f64.const $push[[LIMIT:[0-9]+]]=, 0x1p31{{$}}
|
||||
; CHECK-NEXT: f64.lt $push[[LT:[0-9]+]]=, $pop[[ABS]], $pop[[LIMIT]]{{$}}
|
||||
; CHECK-NEXT: i32.eqz $push[[EQZ:[0-9]+]]=, $pop[[LT]]{{$}}
|
||||
; CHECK-NEXT: br_if 0, $pop[[EQZ]]{{$}}
|
||||
; CHECK-NEXT: i32.trunc_s/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: return $pop[[NUM]]{{$}}
|
||||
; CHECK-NEXT: BB
|
||||
; CHECK-NEXT: end_block
|
||||
; CHECK-NEXT: i32.const $push[[ALT:[0-9]+]]=, -2147483648{{$}}
|
||||
; CHECK-NEXT: return $pop[[ALT]]{{$}}
|
||||
define i32 @i32_trunc_s_f64(double %x) {
|
||||
%a = fptosi double %x to i32
|
||||
ret i32 %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: i32_trunc_u_f64:
|
||||
; CHECK-NEXT: .param f64{{$}}
|
||||
; CHECK-NEXT: .result i32{{$}}
|
||||
; CHECK-NEXT: block
|
||||
; CHECK-NEXT: f64.const $push[[LIMIT:[0-9]+]]=, 0x1p32{{$}}
|
||||
; CHECK-NEXT: f64.lt $push[[LT:[0-9]+]]=, $0, $pop[[LIMIT]]{{$}}
|
||||
; CHECK-NEXT: i32.eqz $push[[EQZ:[0-9]+]]=, $pop[[LT]]{{$}}
|
||||
; CHECK-NEXT: br_if 0, $pop[[EQZ]]{{$}}
|
||||
; CHECK-NEXT: i32.trunc_u/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: return $pop[[NUM]]{{$}}
|
||||
; CHECK-NEXT: BB
|
||||
; CHECK-NEXT: end_block
|
||||
; CHECK-NEXT: i32.const $push[[ALT:[0-9]+]]=, 0{{$}}
|
||||
; CHECK-NEXT: return $pop[[ALT]]{{$}}
|
||||
define i32 @i32_trunc_u_f64(double %x) {
|
||||
%a = fptoui double %x to i32
|
||||
ret i32 %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: i64_trunc_s_f32:
|
||||
; CHECK-NEXT: .param f32{{$}}
|
||||
; CHECK-NEXT: .result i64{{$}}
|
||||
; CHECK-NEXT: block
|
||||
; CHECK-NEXT: f32.abs $push[[ABS:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: f32.const $push[[LIMIT:[0-9]+]]=, 0x1p63{{$}}
|
||||
; CHECK-NEXT: f32.lt $push[[LT:[0-9]+]]=, $pop[[ABS]], $pop[[LIMIT]]{{$}}
|
||||
; CHECK-NEXT: i32.eqz $push[[EQZ:[0-9]+]]=, $pop[[LT]]{{$}}
|
||||
; CHECK-NEXT: br_if 0, $pop[[EQZ]]{{$}}
|
||||
; CHECK-NEXT: i64.trunc_s/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: return $pop[[NUM]]{{$}}
|
||||
; CHECK-NEXT: BB
|
||||
; CHECK-NEXT: end_block
|
||||
; CHECK-NEXT: i64.const $push[[ALT:[0-9]+]]=, -9223372036854775808{{$}}
|
||||
; CHECK-NEXT: return $pop[[ALT]]{{$}}
|
||||
define i64 @i64_trunc_s_f32(float %x) {
|
||||
%a = fptosi float %x to i64
|
||||
ret i64 %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: i64_trunc_u_f32:
|
||||
; CHECK-NEXT: .param f32{{$}}
|
||||
; CHECK-NEXT: .result i64{{$}}
|
||||
; CHECK-NEXT: block
|
||||
; CHECK-NEXT: f32.const $push[[LIMIT:[0-9]+]]=, 0x1p64{{$}}
|
||||
; CHECK-NEXT: f32.lt $push[[LT:[0-9]+]]=, $0, $pop[[LIMIT]]{{$}}
|
||||
; CHECK-NEXT: i32.eqz $push[[EQZ:[0-9]+]]=, $pop[[LT]]{{$}}
|
||||
; CHECK-NEXT: br_if 0, $pop[[EQZ]]{{$}}
|
||||
; CHECK-NEXT: i64.trunc_u/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: return $pop[[NUM]]{{$}}
|
||||
; CHECK-NEXT: BB
|
||||
; CHECK-NEXT: end_block
|
||||
; CHECK-NEXT: i64.const $push[[ALT:[0-9]+]]=, 0{{$}}
|
||||
; CHECK-NEXT: return $pop[[ALT]]{{$}}
|
||||
define i64 @i64_trunc_u_f32(float %x) {
|
||||
%a = fptoui float %x to i64
|
||||
ret i64 %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: i64_trunc_s_f64:
|
||||
; CHECK-NEXT: .param f64{{$}}
|
||||
; CHECK-NEXT: .result i64{{$}}
|
||||
; CHECK-NEXT: block
|
||||
; CHECK-NEXT: f64.abs $push[[ABS:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: f64.const $push[[LIMIT:[0-9]+]]=, 0x1p63{{$}}
|
||||
; CHECK-NEXT: f64.lt $push[[LT:[0-9]+]]=, $pop[[ABS]], $pop[[LIMIT]]{{$}}
|
||||
; CHECK-NEXT: i32.eqz $push[[EQZ:[0-9]+]]=, $pop[[LT]]{{$}}
|
||||
; CHECK-NEXT: br_if 0, $pop[[EQZ]]{{$}}
|
||||
; CHECK-NEXT: i64.trunc_s/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: return $pop[[NUM]]{{$}}
|
||||
; CHECK-NEXT: BB
|
||||
; CHECK-NEXT: end_block
|
||||
; CHECK-NEXT: i64.const $push[[ALT:[0-9]+]]=, -9223372036854775808{{$}}
|
||||
; CHECK-NEXT: return $pop[[ALT]]{{$}}
|
||||
define i64 @i64_trunc_s_f64(double %x) {
|
||||
%a = fptosi double %x to i64
|
||||
ret i64 %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: i64_trunc_u_f64:
|
||||
; CHECK-NEXT: .param f64{{$}}
|
||||
; CHECK-NEXT: .result i64{{$}}
|
||||
; CHECK-NEXT: block
|
||||
; CHECK-NEXT: f64.const $push[[LIMIT:[0-9]+]]=, 0x1p64{{$}}
|
||||
; CHECK-NEXT: f64.lt $push[[LT:[0-9]+]]=, $0, $pop[[LIMIT]]{{$}}
|
||||
; CHECK-NEXT: i32.eqz $push[[EQZ:[0-9]+]]=, $pop[[LT]]{{$}}
|
||||
; CHECK-NEXT: br_if 0, $pop[[EQZ]]{{$}}
|
||||
; CHECK-NEXT: i64.trunc_u/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: return $pop[[NUM]]{{$}}
|
||||
; CHECK-NEXT: BB
|
||||
; CHECK-NEXT: end_block
|
||||
; CHECK-NEXT: i64.const $push[[ALT:[0-9]+]]=, 0{{$}}
|
||||
; CHECK-NEXT: return $pop[[ALT]]{{$}}
|
||||
define i64 @i64_trunc_u_f64(double %x) {
|
||||
%a = fptoui double %x to i64
|
||||
ret i64 %a
|
||||
}
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals | FileCheck %s
|
||||
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+nontrapping-fptoint | FileCheck %s
|
||||
|
||||
; Test that basic conversion operations assemble as expected.
|
||||
|
||||
@ -38,7 +38,7 @@ define i64 @i64_extend_u_i32(i32 %x) {
|
||||
; CHECK-LABEL: i32_trunc_s_f32:
|
||||
; CHECK-NEXT: .param f32{{$}}
|
||||
; CHECK-NEXT: .result i32{{$}}
|
||||
; CHECK-NEXT: i32.trunc_s/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: i32.trunc_s:sat/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: return $pop[[NUM]]{{$}}
|
||||
define i32 @i32_trunc_s_f32(float %x) {
|
||||
%a = fptosi float %x to i32
|
||||
@ -48,7 +48,7 @@ define i32 @i32_trunc_s_f32(float %x) {
|
||||
; CHECK-LABEL: i32_trunc_u_f32:
|
||||
; CHECK-NEXT: .param f32{{$}}
|
||||
; CHECK-NEXT: .result i32{{$}}
|
||||
; CHECK-NEXT: i32.trunc_u/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: i32.trunc_u:sat/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: return $pop[[NUM]]{{$}}
|
||||
define i32 @i32_trunc_u_f32(float %x) {
|
||||
%a = fptoui float %x to i32
|
||||
@ -58,7 +58,7 @@ define i32 @i32_trunc_u_f32(float %x) {
|
||||
; CHECK-LABEL: i32_trunc_s_f64:
|
||||
; CHECK-NEXT: .param f64{{$}}
|
||||
; CHECK-NEXT: .result i32{{$}}
|
||||
; CHECK-NEXT: i32.trunc_s/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: i32.trunc_s:sat/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: return $pop[[NUM]]{{$}}
|
||||
define i32 @i32_trunc_s_f64(double %x) {
|
||||
%a = fptosi double %x to i32
|
||||
@ -68,7 +68,7 @@ define i32 @i32_trunc_s_f64(double %x) {
|
||||
; CHECK-LABEL: i32_trunc_u_f64:
|
||||
; CHECK-NEXT: .param f64{{$}}
|
||||
; CHECK-NEXT: .result i32{{$}}
|
||||
; CHECK-NEXT: i32.trunc_u/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: i32.trunc_u:sat/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: return $pop[[NUM]]{{$}}
|
||||
define i32 @i32_trunc_u_f64(double %x) {
|
||||
%a = fptoui double %x to i32
|
||||
@ -78,7 +78,7 @@ define i32 @i32_trunc_u_f64(double %x) {
|
||||
; CHECK-LABEL: i64_trunc_s_f32:
|
||||
; CHECK-NEXT: .param f32{{$}}
|
||||
; CHECK-NEXT: .result i64{{$}}
|
||||
; CHECK-NEXT: i64.trunc_s/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: i64.trunc_s:sat/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: return $pop[[NUM]]{{$}}
|
||||
define i64 @i64_trunc_s_f32(float %x) {
|
||||
%a = fptosi float %x to i64
|
||||
@ -88,7 +88,7 @@ define i64 @i64_trunc_s_f32(float %x) {
|
||||
; CHECK-LABEL: i64_trunc_u_f32:
|
||||
; CHECK-NEXT: .param f32{{$}}
|
||||
; CHECK-NEXT: .result i64{{$}}
|
||||
; CHECK-NEXT: i64.trunc_u/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: i64.trunc_u:sat/f32 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: return $pop[[NUM]]{{$}}
|
||||
define i64 @i64_trunc_u_f32(float %x) {
|
||||
%a = fptoui float %x to i64
|
||||
@ -98,7 +98,7 @@ define i64 @i64_trunc_u_f32(float %x) {
|
||||
; CHECK-LABEL: i64_trunc_s_f64:
|
||||
; CHECK-NEXT: .param f64{{$}}
|
||||
; CHECK-NEXT: .result i64{{$}}
|
||||
; CHECK-NEXT: i64.trunc_s/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: i64.trunc_s:sat/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: return $pop[[NUM]]{{$}}
|
||||
define i64 @i64_trunc_s_f64(double %x) {
|
||||
%a = fptosi double %x to i64
|
||||
@ -108,7 +108,7 @@ define i64 @i64_trunc_s_f64(double %x) {
|
||||
; CHECK-LABEL: i64_trunc_u_f64:
|
||||
; CHECK-NEXT: .param f64{{$}}
|
||||
; CHECK-NEXT: .result i64{{$}}
|
||||
; CHECK-NEXT: i64.trunc_u/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: i64.trunc_u:sat/f64 $push[[NUM:[0-9]+]]=, $0{{$}}
|
||||
; CHECK-NEXT: return $pop[[NUM]]{{$}}
|
||||
define i64 @i64_trunc_u_f64(double %x) {
|
||||
%a = fptoui double %x to i64
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user