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[libunwind][RISCV] Add 64-bit RISC-V support
Summary: Add unwinding support for 64-bit RISC-V. This is from the FreeBSD implementation with the following minor changes: - Renamed and renumbered DWARF registers to match the RISC-V ABI [1] - Use the ABI mneumonics in getRegisterName() instead of the exact register names - Include checks for __riscv_xlen == 64 to facilitate adding the 32-bit ABI in the future. [1] https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md Patch by Mitchell Horne (mhorne) Reviewers: lenary, luismarques, compnerd, phosek Reviewed By: lenary, luismarques Subscribers: arichardson, sameer.abuasal, abidh, asb, aprantl, krytarowski, simoncook, kito-cheng, christof, shiva0217, rogfer01, rkruppe, PkmX, psnobl, benna, lenary, s.egerton, luismarques, emaste, cfe-commits Differential Revision: https://reviews.llvm.org/D68362
This commit is contained in:
Sam Elliott
parent
055aeb5275
commit
ce3d1c6d61
@ -23,6 +23,7 @@
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K 32
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS 65
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV 64
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#if defined(_LIBUNWIND_IS_NATIVE_ONLY)
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# if defined(__i386__)
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@ -118,6 +119,15 @@
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#define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC
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#define _LIBUNWIND_CONTEXT_SIZE 16
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#define _LIBUNWIND_CURSOR_SIZE 23
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# elif defined(__riscv)
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# if __riscv_xlen == 64
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# define _LIBUNWIND_TARGET_RISCV 1
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# define _LIBUNWIND_CONTEXT_SIZE 64
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# define _LIBUNWIND_CURSOR_SIZE 76
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# else
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# error "Unsupported RISC-V ABI"
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# endif
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV
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# else
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# error "Unsupported architecture."
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# endif
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@ -132,6 +142,7 @@
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# define _LIBUNWIND_TARGET_MIPS_O32 1
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# define _LIBUNWIND_TARGET_MIPS_NEWABI 1
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# define _LIBUNWIND_TARGET_SPARC 1
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# define _LIBUNWIND_TARGET_RISCV 1
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# define _LIBUNWIND_CONTEXT_SIZE 167
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# define _LIBUNWIND_CURSOR_SIZE 179
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# define _LIBUNWIND_HIGHEST_DWARF_REGISTER 287
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@ -832,4 +832,75 @@ enum {
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UNW_SPARC_I7 = 31,
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};
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// RISC-V registers. These match the DWARF register numbers defined by section
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// 4 of the RISC-V ELF psABI specification, which can be found at:
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//
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// https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
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enum {
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UNW_RISCV_X0 = 0,
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UNW_RISCV_X1 = 1,
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UNW_RISCV_X2 = 2,
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UNW_RISCV_X3 = 3,
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UNW_RISCV_X4 = 4,
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UNW_RISCV_X5 = 5,
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UNW_RISCV_X6 = 6,
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UNW_RISCV_X7 = 7,
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UNW_RISCV_X8 = 8,
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UNW_RISCV_X9 = 9,
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UNW_RISCV_X10 = 10,
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UNW_RISCV_X11 = 11,
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UNW_RISCV_X12 = 12,
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UNW_RISCV_X13 = 13,
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UNW_RISCV_X14 = 14,
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UNW_RISCV_X15 = 15,
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UNW_RISCV_X16 = 16,
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UNW_RISCV_X17 = 17,
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UNW_RISCV_X18 = 18,
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UNW_RISCV_X19 = 19,
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UNW_RISCV_X20 = 20,
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UNW_RISCV_X21 = 21,
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UNW_RISCV_X22 = 22,
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UNW_RISCV_X23 = 23,
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UNW_RISCV_X24 = 24,
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UNW_RISCV_X25 = 25,
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UNW_RISCV_X26 = 26,
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UNW_RISCV_X27 = 27,
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UNW_RISCV_X28 = 28,
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UNW_RISCV_X29 = 29,
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UNW_RISCV_X30 = 30,
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UNW_RISCV_X31 = 31,
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UNW_RISCV_F0 = 32,
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UNW_RISCV_F1 = 33,
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UNW_RISCV_F2 = 34,
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UNW_RISCV_F3 = 35,
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UNW_RISCV_F4 = 36,
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UNW_RISCV_F5 = 37,
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UNW_RISCV_F6 = 38,
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UNW_RISCV_F7 = 39,
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UNW_RISCV_F8 = 40,
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UNW_RISCV_F9 = 41,
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UNW_RISCV_F10 = 42,
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UNW_RISCV_F11 = 43,
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UNW_RISCV_F12 = 44,
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UNW_RISCV_F13 = 45,
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UNW_RISCV_F14 = 46,
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UNW_RISCV_F15 = 47,
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UNW_RISCV_F16 = 48,
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UNW_RISCV_F17 = 49,
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UNW_RISCV_F18 = 50,
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UNW_RISCV_F19 = 51,
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UNW_RISCV_F20 = 52,
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UNW_RISCV_F21 = 53,
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UNW_RISCV_F22 = 54,
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UNW_RISCV_F23 = 55,
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UNW_RISCV_F24 = 56,
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UNW_RISCV_F25 = 57,
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UNW_RISCV_F26 = 58,
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UNW_RISCV_F27 = 59,
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UNW_RISCV_F28 = 60,
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UNW_RISCV_F29 = 61,
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UNW_RISCV_F30 = 62,
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UNW_RISCV_F31 = 63,
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};
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#endif
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@ -34,6 +34,7 @@ enum {
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REGISTERS_MIPS_O32,
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REGISTERS_MIPS_NEWABI,
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REGISTERS_SPARC,
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REGISTERS_RISCV,
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};
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#if defined(_LIBUNWIND_TARGET_I386)
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@ -3517,6 +3518,270 @@ inline const char *Registers_sparc::getRegisterName(int regNum) {
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}
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#endif // _LIBUNWIND_TARGET_SPARC
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#if defined(_LIBUNWIND_TARGET_RISCV)
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/// Registers_riscv holds the register state of a thread in a 64-bit RISC-V
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/// process.
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class _LIBUNWIND_HIDDEN Registers_riscv {
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public:
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Registers_riscv();
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Registers_riscv(const void *registers);
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bool validRegister(int num) const;
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uint64_t getRegister(int num) const;
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void setRegister(int num, uint64_t value);
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bool validFloatRegister(int num) const;
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double getFloatRegister(int num) const;
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void setFloatRegister(int num, double value);
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bool validVectorRegister(int num) const;
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v128 getVectorRegister(int num) const;
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void setVectorRegister(int num, v128 value);
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static const char *getRegisterName(int num);
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void jumpto();
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static int lastDwarfRegNum() { return _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV; }
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static int getArch() { return REGISTERS_RISCV; }
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uint64_t getSP() const { return _registers[2]; }
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void setSP(uint64_t value) { _registers[2] = value; }
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uint64_t getIP() const { return _registers[1]; }
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void setIP(uint64_t value) { _registers[1] = value; }
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private:
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uint64_t _registers[32];
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double _floats[32];
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};
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inline Registers_riscv::Registers_riscv(const void *registers) {
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static_assert((check_fit<Registers_riscv, unw_context_t>::does_fit),
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"riscv registers do not fit into unw_context_t");
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memcpy(&_registers, registers, sizeof(_registers));
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static_assert(sizeof(_registers) == 0x100,
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"expected float registers to be at offset 256");
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memcpy(_floats,
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static_cast<const uint8_t *>(registers) + sizeof(_registers),
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sizeof(_floats));
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}
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inline Registers_riscv::Registers_riscv() {
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memset(&_registers, 0, sizeof(_registers));
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memset(&_floats, 0, sizeof(_floats));
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}
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inline bool Registers_riscv::validRegister(int regNum) const {
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if (regNum == UNW_REG_IP)
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return true;
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if (regNum == UNW_REG_SP)
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return true;
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if (regNum < 0)
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return false;
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if (regNum > UNW_RISCV_F31)
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return false;
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return true;
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}
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inline uint64_t Registers_riscv::getRegister(int regNum) const {
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if (regNum == UNW_REG_IP)
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return _registers[1];
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if (regNum == UNW_REG_SP)
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return _registers[2];
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if (regNum == UNW_RISCV_X0)
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return 0;
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if ((regNum > 0) && (regNum < 32))
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return _registers[regNum];
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_LIBUNWIND_ABORT("unsupported riscv register");
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}
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inline void Registers_riscv::setRegister(int regNum, uint64_t value) {
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if (regNum == UNW_REG_IP)
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_registers[1] = value;
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else if (regNum == UNW_REG_SP)
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_registers[2] = value;
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else if (regNum == UNW_RISCV_X0)
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/* x0 is hardwired to zero */
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return;
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else if ((regNum > 0) && (regNum < 32))
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_registers[regNum] = value;
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else
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_LIBUNWIND_ABORT("unsupported riscv register");
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}
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inline const char *Registers_riscv::getRegisterName(int regNum) {
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switch (regNum) {
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case UNW_REG_IP:
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return "pc";
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case UNW_REG_SP:
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return "sp";
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case UNW_RISCV_X0:
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return "zero";
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case UNW_RISCV_X1:
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return "ra";
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case UNW_RISCV_X2:
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return "sp";
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case UNW_RISCV_X3:
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return "gp";
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case UNW_RISCV_X4:
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return "tp";
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case UNW_RISCV_X5:
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return "t0";
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case UNW_RISCV_X6:
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return "t1";
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case UNW_RISCV_X7:
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return "t2";
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case UNW_RISCV_X8:
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return "s0";
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case UNW_RISCV_X9:
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return "s1";
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case UNW_RISCV_X10:
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return "a0";
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case UNW_RISCV_X11:
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return "a1";
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case UNW_RISCV_X12:
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return "a2";
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case UNW_RISCV_X13:
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return "a3";
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case UNW_RISCV_X14:
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return "a4";
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case UNW_RISCV_X15:
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return "a5";
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case UNW_RISCV_X16:
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return "a6";
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case UNW_RISCV_X17:
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return "a7";
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case UNW_RISCV_X18:
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return "s2";
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case UNW_RISCV_X19:
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return "s3";
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case UNW_RISCV_X20:
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return "s4";
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case UNW_RISCV_X21:
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return "s5";
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case UNW_RISCV_X22:
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return "s6";
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case UNW_RISCV_X23:
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return "s7";
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case UNW_RISCV_X24:
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return "s8";
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case UNW_RISCV_X25:
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return "s9";
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case UNW_RISCV_X26:
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return "s10";
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case UNW_RISCV_X27:
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return "s11";
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case UNW_RISCV_X28:
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return "t3";
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case UNW_RISCV_X29:
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return "t4";
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case UNW_RISCV_X30:
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return "t5";
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case UNW_RISCV_X31:
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return "t6";
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case UNW_RISCV_F0:
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return "ft0";
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case UNW_RISCV_F1:
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return "ft1";
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case UNW_RISCV_F2:
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return "ft2";
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case UNW_RISCV_F3:
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return "ft3";
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case UNW_RISCV_F4:
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return "ft4";
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case UNW_RISCV_F5:
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return "ft5";
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case UNW_RISCV_F6:
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return "ft6";
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case UNW_RISCV_F7:
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return "ft7";
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case UNW_RISCV_F8:
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return "fs0";
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case UNW_RISCV_F9:
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return "fs1";
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case UNW_RISCV_F10:
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return "fa0";
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case UNW_RISCV_F11:
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return "fa1";
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case UNW_RISCV_F12:
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return "fa2";
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case UNW_RISCV_F13:
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return "fa3";
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case UNW_RISCV_F14:
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return "fa4";
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case UNW_RISCV_F15:
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return "fa5";
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case UNW_RISCV_F16:
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return "fa6";
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case UNW_RISCV_F17:
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return "fa7";
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case UNW_RISCV_F18:
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return "fs2";
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case UNW_RISCV_F19:
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return "fs3";
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case UNW_RISCV_F20:
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return "fs4";
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case UNW_RISCV_F21:
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return "fs5";
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case UNW_RISCV_F22:
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return "fs6";
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case UNW_RISCV_F23:
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return "fs7";
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case UNW_RISCV_F24:
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return "fs8";
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case UNW_RISCV_F25:
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return "fs9";
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case UNW_RISCV_F26:
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return "fs10";
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case UNW_RISCV_F27:
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return "fs11";
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case UNW_RISCV_F28:
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return "ft8";
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case UNW_RISCV_F29:
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return "ft9";
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case UNW_RISCV_F30:
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return "ft10";
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case UNW_RISCV_F31:
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return "ft11";
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default:
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return "unknown register";
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}
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}
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inline bool Registers_riscv::validFloatRegister(int regNum) const {
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if (regNum < UNW_RISCV_F0)
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return false;
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if (regNum > UNW_RISCV_F31)
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return false;
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return true;
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}
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inline double Registers_riscv::getFloatRegister(int regNum) const {
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#if defined(__riscv_flen) && __riscv_flen == 64
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assert(validFloatRegister(regNum));
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return _floats[regNum - UNW_RISCV_F0];
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#else
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_LIBUNWIND_ABORT("libunwind not built with float support");
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#endif
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}
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inline void Registers_riscv::setFloatRegister(int regNum, double value) {
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#if defined(__riscv_flen) && __riscv_flen == 64
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assert(validFloatRegister(regNum));
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_floats[regNum - UNW_RISCV_F0] = value;
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#else
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_LIBUNWIND_ABORT("libunwind not built with float support");
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#endif
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}
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inline bool Registers_riscv::validVectorRegister(int) const {
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return false;
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}
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inline v128 Registers_riscv::getVectorRegister(int) const {
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_LIBUNWIND_ABORT("no riscv vector register support yet");
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}
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inline void Registers_riscv::setVectorRegister(int, v128) {
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_LIBUNWIND_ABORT("no riscv vector register support yet");
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}
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#endif // _LIBUNWIND_TARGET_RISCV
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} // namespace libunwind
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#endif // __REGISTERS_HPP__
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@ -995,6 +995,12 @@ private:
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int stepWithCompactEncoding(Registers_sparc &) { return UNW_EINVAL; }
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#endif
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#if defined (_LIBUNWIND_TARGET_RISCV)
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int stepWithCompactEncoding(Registers_riscv &) {
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return UNW_EINVAL;
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}
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#endif
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bool compactSaysUseDwarf(uint32_t *offset=NULL) const {
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R dummy;
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return compactSaysUseDwarf(dummy, offset);
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@ -1061,6 +1067,12 @@ private:
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bool compactSaysUseDwarf(Registers_sparc &, uint32_t *) const { return true; }
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#endif
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#if defined (_LIBUNWIND_TARGET_RISCV)
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bool compactSaysUseDwarf(Registers_riscv &, uint32_t *) const {
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return true;
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}
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#endif
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#endif // defined(_LIBUNWIND_SUPPORT_COMPACT_UNWIND)
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#if defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND)
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@ -1127,6 +1139,12 @@ private:
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compact_unwind_encoding_t dwarfEncoding(Registers_sparc &) const { return 0; }
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#endif
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#if defined (_LIBUNWIND_TARGET_RISCV)
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compact_unwind_encoding_t dwarfEncoding(Registers_riscv &) const {
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return 0;
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}
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#endif
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#endif // defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND)
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|
||||
#if defined(_LIBUNWIND_SUPPORT_SEH_UNWIND)
|
||||
|
||||
@ -1029,6 +1029,87 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_sparc6jumptoEv)
|
||||
jmp %o7
|
||||
nop
|
||||
|
||||
#elif defined(__riscv) && __riscv_xlen == 64
|
||||
|
||||
//
|
||||
// void libunwind::Registers_riscv::jumpto()
|
||||
//
|
||||
// On entry:
|
||||
// thread_state pointer is in a0
|
||||
//
|
||||
.p2align 2
|
||||
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_riscv6jumptoEv)
|
||||
#if defined(__riscv_flen) && __riscv_flen == 64
|
||||
fld f0, (8 * 32 + 8 * 0)(a0)
|
||||
fld f1, (8 * 32 + 8 * 1)(a0)
|
||||
fld f2, (8 * 32 + 8 * 2)(a0)
|
||||
fld f3, (8 * 32 + 8 * 3)(a0)
|
||||
fld f4, (8 * 32 + 8 * 4)(a0)
|
||||
fld f5, (8 * 32 + 8 * 5)(a0)
|
||||
fld f6, (8 * 32 + 8 * 6)(a0)
|
||||
fld f7, (8 * 32 + 8 * 7)(a0)
|
||||
fld f8, (8 * 32 + 8 * 8)(a0)
|
||||
fld f9, (8 * 32 + 8 * 9)(a0)
|
||||
fld f10, (8 * 32 + 8 * 10)(a0)
|
||||
fld f11, (8 * 32 + 8 * 11)(a0)
|
||||
fld f12, (8 * 32 + 8 * 12)(a0)
|
||||
fld f13, (8 * 32 + 8 * 13)(a0)
|
||||
fld f14, (8 * 32 + 8 * 14)(a0)
|
||||
fld f15, (8 * 32 + 8 * 15)(a0)
|
||||
fld f16, (8 * 32 + 8 * 16)(a0)
|
||||
fld f17, (8 * 32 + 8 * 17)(a0)
|
||||
fld f18, (8 * 32 + 8 * 18)(a0)
|
||||
fld f19, (8 * 32 + 8 * 19)(a0)
|
||||
fld f20, (8 * 32 + 8 * 20)(a0)
|
||||
fld f21, (8 * 32 + 8 * 21)(a0)
|
||||
fld f22, (8 * 32 + 8 * 22)(a0)
|
||||
fld f23, (8 * 32 + 8 * 23)(a0)
|
||||
fld f24, (8 * 32 + 8 * 24)(a0)
|
||||
fld f25, (8 * 32 + 8 * 25)(a0)
|
||||
fld f26, (8 * 32 + 8 * 26)(a0)
|
||||
fld f27, (8 * 32 + 8 * 27)(a0)
|
||||
fld f28, (8 * 32 + 8 * 28)(a0)
|
||||
fld f29, (8 * 32 + 8 * 29)(a0)
|
||||
fld f30, (8 * 32 + 8 * 30)(a0)
|
||||
fld f31, (8 * 32 + 8 * 31)(a0)
|
||||
#endif
|
||||
|
||||
// x0 is zero
|
||||
ld x1, (8 * 1)(a0)
|
||||
ld x2, (8 * 2)(a0)
|
||||
ld x3, (8 * 3)(a0)
|
||||
ld x4, (8 * 4)(a0)
|
||||
ld x5, (8 * 5)(a0)
|
||||
ld x6, (8 * 6)(a0)
|
||||
ld x7, (8 * 7)(a0)
|
||||
ld x8, (8 * 8)(a0)
|
||||
ld x9, (8 * 9)(a0)
|
||||
// skip a0 for now
|
||||
ld x11, (8 * 11)(a0)
|
||||
ld x12, (8 * 12)(a0)
|
||||
ld x13, (8 * 13)(a0)
|
||||
ld x14, (8 * 14)(a0)
|
||||
ld x15, (8 * 15)(a0)
|
||||
ld x16, (8 * 16)(a0)
|
||||
ld x17, (8 * 17)(a0)
|
||||
ld x18, (8 * 18)(a0)
|
||||
ld x19, (8 * 19)(a0)
|
||||
ld x20, (8 * 20)(a0)
|
||||
ld x21, (8 * 21)(a0)
|
||||
ld x22, (8 * 22)(a0)
|
||||
ld x23, (8 * 23)(a0)
|
||||
ld x24, (8 * 24)(a0)
|
||||
ld x25, (8 * 25)(a0)
|
||||
ld x26, (8 * 26)(a0)
|
||||
ld x27, (8 * 27)(a0)
|
||||
ld x28, (8 * 28)(a0)
|
||||
ld x29, (8 * 29)(a0)
|
||||
ld x30, (8 * 30)(a0)
|
||||
ld x31, (8 * 31)(a0)
|
||||
ld x10, (8 * 10)(a0) // restore a0
|
||||
|
||||
ret // jump to ra
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* !defined(__USING_SJLJ_EXCEPTIONS__) */
|
||||
|
||||
@ -974,6 +974,86 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
|
||||
std %i6, [%o0 + 120]
|
||||
jmp %o7
|
||||
clr %o0 // return UNW_ESUCCESS
|
||||
|
||||
#elif defined(__riscv) && __riscv_xlen == 64
|
||||
|
||||
#
|
||||
# extern int __unw_getcontext(unw_context_t* thread_state)
|
||||
#
|
||||
# On entry:
|
||||
# thread_state pointer is in a0
|
||||
#
|
||||
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
|
||||
// x0 is zero
|
||||
sd x1, (8 * 1)(a0)
|
||||
sd x2, (8 * 2)(a0)
|
||||
sd x3, (8 * 3)(a0)
|
||||
sd x4, (8 * 4)(a0)
|
||||
sd x5, (8 * 5)(a0)
|
||||
sd x6, (8 * 6)(a0)
|
||||
sd x7, (8 * 7)(a0)
|
||||
sd x8, (8 * 8)(a0)
|
||||
sd x9, (8 * 9)(a0)
|
||||
sd x10, (8 * 10)(a0)
|
||||
sd x11, (8 * 11)(a0)
|
||||
sd x12, (8 * 12)(a0)
|
||||
sd x13, (8 * 13)(a0)
|
||||
sd x14, (8 * 14)(a0)
|
||||
sd x15, (8 * 15)(a0)
|
||||
sd x16, (8 * 16)(a0)
|
||||
sd x17, (8 * 17)(a0)
|
||||
sd x18, (8 * 18)(a0)
|
||||
sd x19, (8 * 19)(a0)
|
||||
sd x20, (8 * 20)(a0)
|
||||
sd x21, (8 * 21)(a0)
|
||||
sd x22, (8 * 22)(a0)
|
||||
sd x23, (8 * 23)(a0)
|
||||
sd x24, (8 * 24)(a0)
|
||||
sd x25, (8 * 25)(a0)
|
||||
sd x26, (8 * 26)(a0)
|
||||
sd x27, (8 * 27)(a0)
|
||||
sd x28, (8 * 28)(a0)
|
||||
sd x29, (8 * 29)(a0)
|
||||
sd x30, (8 * 30)(a0)
|
||||
sd x31, (8 * 31)(a0)
|
||||
|
||||
#if defined(__riscv_flen) && __riscv_flen == 64
|
||||
fsd f0, (8 * 32 + 8 * 0)(a0)
|
||||
fsd f1, (8 * 32 + 8 * 1)(a0)
|
||||
fsd f2, (8 * 32 + 8 * 2)(a0)
|
||||
fsd f3, (8 * 32 + 8 * 3)(a0)
|
||||
fsd f4, (8 * 32 + 8 * 4)(a0)
|
||||
fsd f5, (8 * 32 + 8 * 5)(a0)
|
||||
fsd f6, (8 * 32 + 8 * 6)(a0)
|
||||
fsd f7, (8 * 32 + 8 * 7)(a0)
|
||||
fsd f8, (8 * 32 + 8 * 8)(a0)
|
||||
fsd f9, (8 * 32 + 8 * 9)(a0)
|
||||
fsd f10, (8 * 32 + 8 * 10)(a0)
|
||||
fsd f11, (8 * 32 + 8 * 11)(a0)
|
||||
fsd f12, (8 * 32 + 8 * 12)(a0)
|
||||
fsd f13, (8 * 32 + 8 * 13)(a0)
|
||||
fsd f14, (8 * 32 + 8 * 14)(a0)
|
||||
fsd f15, (8 * 32 + 8 * 15)(a0)
|
||||
fsd f16, (8 * 32 + 8 * 16)(a0)
|
||||
fsd f17, (8 * 32 + 8 * 17)(a0)
|
||||
fsd f18, (8 * 32 + 8 * 18)(a0)
|
||||
fsd f19, (8 * 32 + 8 * 19)(a0)
|
||||
fsd f20, (8 * 32 + 8 * 20)(a0)
|
||||
fsd f21, (8 * 32 + 8 * 21)(a0)
|
||||
fsd f22, (8 * 32 + 8 * 22)(a0)
|
||||
fsd f23, (8 * 32 + 8 * 23)(a0)
|
||||
fsd f24, (8 * 32 + 8 * 24)(a0)
|
||||
fsd f25, (8 * 32 + 8 * 25)(a0)
|
||||
fsd f26, (8 * 32 + 8 * 26)(a0)
|
||||
fsd f27, (8 * 32 + 8 * 27)(a0)
|
||||
fsd f28, (8 * 32 + 8 * 28)(a0)
|
||||
fsd f29, (8 * 32 + 8 * 29)(a0)
|
||||
fsd f30, (8 * 32 + 8 * 30)(a0)
|
||||
fsd f31, (8 * 32 + 8 * 31)(a0)
|
||||
#endif
|
||||
|
||||
li a0, 0 // return UNW_ESUCCESS
|
||||
ret // jump to ra
|
||||
#endif
|
||||
|
||||
WEAK_ALIAS(__unw_getcontext, unw_getcontext)
|
||||
|
||||
@ -103,7 +103,8 @@
|
||||
defined(__ppc__) || defined(__ppc64__) || defined(__powerpc64__) || \
|
||||
(!defined(__APPLE__) && defined(__arm__)) || \
|
||||
(defined(__arm64__) || defined(__aarch64__)) || \
|
||||
defined(__mips__)
|
||||
defined(__mips__) || \
|
||||
defined(__riscv)
|
||||
#if !defined(_LIBUNWIND_BUILD_SJLJ_APIS)
|
||||
#define _LIBUNWIND_BUILD_ZERO_COST_APIS
|
||||
#endif
|
||||
|
||||
@ -58,6 +58,8 @@ _LIBUNWIND_HIDDEN int __unw_init_local(unw_cursor_t *cursor,
|
||||
# warning The MIPS architecture is not supported with this ABI and environment!
|
||||
#elif defined(__sparc__)
|
||||
# define REGISTER_KIND Registers_sparc
|
||||
#elif defined(__riscv) && __riscv_xlen == 64
|
||||
# define REGISTER_KIND Registers_riscv
|
||||
#else
|
||||
# error Architecture not supported
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user