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[AArch64][GlobalISel] Select CSINC and CSINV for G_SELECT with constants
Select the following: - G_SELECT cc, 0, 1 -> CSINC zreg, zreg, cc - G_SELECT cc 0, -1 -> CSINV zreg, zreg cc - G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc - G_SELECT cc, -1, f -> CSINV f, zreg, inv_cc - G_SELECT cc, t, 1 -> CSINC t, zreg, cc - G_SELECT cc, t, -1 -> CSINC t, zreg, cc (IR example: https://godbolt.org/z/YfPna9) These correspond to a bunch of the AArch64csel patterns in AArch64InstrInfo.td. Unfortunately, it doesn't seem like we can import patterns that use NZCV like those ones do. E.g. ``` def : Pat<(AArch64csel GPR32:$tval, (i32 1), (i32 imm:$cc), NZCV), (CSINCWr GPR32:$tval, WZR, (i32 imm:$cc))>; ``` So we have to manually select these for now. This replaces `selectSelectOpc` with an `emitSelect` function, which performs these optimizations. Differential Revision: https://reviews.llvm.org/D90701
This commit is contained in:
Jessica Paquette
parent
410626c9b5
commit
d0ba6c4002
@ -225,6 +225,9 @@ private:
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitTST(MachineOperand &LHS, MachineOperand &RHS,
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitSelect(Register Dst, Register LHS, Register RHS,
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AArch64CC::CondCode CC,
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitExtractVectorElt(Optional<Register> DstReg,
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const RegisterBank &DstRB, LLT ScalarTy,
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Register VecReg, unsigned LaneIdx,
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@ -983,17 +986,107 @@ static unsigned selectFPConvOpc(unsigned GenericOpc, LLT DstTy, LLT SrcTy) {
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return GenericOpc;
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}
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static unsigned selectSelectOpc(MachineInstr &I, MachineRegisterInfo &MRI,
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const RegisterBankInfo &RBI) {
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const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
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bool IsFP = (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() !=
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AArch64::GPRRegBankID);
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LLT Ty = MRI.getType(I.getOperand(0).getReg());
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if (Ty == LLT::scalar(32))
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return IsFP ? AArch64::FCSELSrrr : AArch64::CSELWr;
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else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64))
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return IsFP ? AArch64::FCSELDrrr : AArch64::CSELXr;
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return 0;
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MachineInstr *
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AArch64InstructionSelector::emitSelect(Register Dst, Register True,
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Register False, AArch64CC::CondCode CC,
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MachineIRBuilder &MIB) const {
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MachineRegisterInfo &MRI = *MIB.getMRI();
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assert(RBI.getRegBank(False, MRI, TRI)->getID() ==
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RBI.getRegBank(True, MRI, TRI)->getID() &&
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"Expected both select operands to have the same regbank?");
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LLT Ty = MRI.getType(True);
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if (Ty.isVector())
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return nullptr;
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const unsigned Size = Ty.getSizeInBits();
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assert((Size == 32 || Size == 64) &&
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"Expected 32 bit or 64 bit select only?");
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const bool Is32Bit = Size == 32;
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if (RBI.getRegBank(True, MRI, TRI)->getID() != AArch64::GPRRegBankID) {
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unsigned Opc = Is32Bit ? AArch64::FCSELSrrr : AArch64::FCSELDrrr;
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auto FCSel = MIB.buildInstr(Opc, {Dst}, {True, False}).addImm(CC);
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constrainSelectedInstRegOperands(*FCSel, TII, TRI, RBI);
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return &*FCSel;
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}
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// By default, we'll try and emit a CSEL.
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unsigned Opc = Is32Bit ? AArch64::CSELWr : AArch64::CSELXr;
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// Helper lambda which tries to use CSINC/CSINV for the instruction when its
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// true/false values are constants.
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// FIXME: All of these patterns already exist in tablegen. We should be
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// able to import these.
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auto TryOptSelectCst = [&Opc, &True, &False, &CC, Is32Bit, &MRI]() {
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auto TrueCst = getConstantVRegValWithLookThrough(True, MRI);
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auto FalseCst = getConstantVRegValWithLookThrough(False, MRI);
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if (!TrueCst && !FalseCst)
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return false;
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Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
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if (TrueCst && FalseCst) {
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auto T = TrueCst->Value;
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auto F = FalseCst->Value;
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if (T == 0 && F == 1) {
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// G_SELECT cc, 0, 1 -> CSINC zreg, zreg, cc
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Opc = Is32Bit ? AArch64::CSINCWr : AArch64::CSINCXr;
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True = ZReg;
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False = ZReg;
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return true;
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}
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if (T == 0 && F == -1) {
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// G_SELECT cc 0, -1 -> CSINV zreg, zreg cc
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Opc = Is32Bit ? AArch64::CSINVWr : AArch64::CSINVXr;
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True = ZReg;
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False = ZReg;
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return true;
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}
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}
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if (TrueCst) {
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auto T = TrueCst->Value;
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if (T == 1) {
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// G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
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Opc = Is32Bit ? AArch64::CSINCWr : AArch64::CSINCXr;
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True = False;
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False = ZReg;
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CC = AArch64CC::getInvertedCondCode(CC);
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return true;
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}
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if (T == -1) {
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// G_SELECT cc, -1, f -> CSINV f, zreg, inv_cc
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Opc = Is32Bit ? AArch64::CSINVWr : AArch64::CSINVXr;
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True = False;
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False = ZReg;
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CC = AArch64CC::getInvertedCondCode(CC);
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return true;
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}
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}
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if (FalseCst) {
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auto F = FalseCst->Value;
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if (F == 1) {
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// G_SELECT cc, t, 1 -> CSINC t, zreg, cc
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Opc = Is32Bit ? AArch64::CSINCWr : AArch64::CSINCXr;
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False = ZReg;
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return true;
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}
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if (F == -1) {
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// G_SELECT cc, t, -1 -> CSINC t, zreg, cc
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Opc = Is32Bit ? AArch64::CSINVWr : AArch64::CSINVXr;
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False = ZReg;
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return true;
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}
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}
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return false;
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};
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TryOptSelectCst();
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auto SelectInst = MIB.buildInstr(Opc, {Dst}, {True, False}).addImm(CC);
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constrainSelectedInstRegOperands(*SelectInst, TII, TRI, RBI);
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return &*SelectInst;
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}
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/// Returns true if \p P is an unsigned integer comparison predicate.
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@ -2831,25 +2924,15 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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if (tryOptSelect(I))
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return true;
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Register CSelOpc = selectSelectOpc(I, MRI, RBI);
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// Make sure to use an unused vreg instead of wzr, so that the peephole
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// optimizations will be able to optimize these.
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MachineIRBuilder MIB(I);
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Register DeadVReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
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MachineInstr &TstMI =
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*BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri))
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.addDef(DeadVReg)
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.addUse(CondReg)
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.addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
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MachineInstr &CSelMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CSelOpc))
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.addDef(I.getOperand(0).getReg())
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.addUse(TReg)
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.addUse(FReg)
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.addImm(AArch64CC::NE);
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constrainSelectedInstRegOperands(TstMI, TII, TRI, RBI);
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constrainSelectedInstRegOperands(CSelMI, TII, TRI, RBI);
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auto TstMI = MIB.buildInstr(AArch64::ANDSWri, {DeadVReg}, {CondReg})
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.addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
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constrainSelectedInstRegOperands(*TstMI, TII, TRI, RBI);
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if (!emitSelect(I.getOperand(0).getReg(), TReg, FReg, AArch64CC::NE, MIB))
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return false;
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I.eraseFromParent();
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return true;
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}
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@ -4132,9 +4215,6 @@ AArch64InstructionSelector::emitCSetForICMP(Register DefReg, unsigned Pred,
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bool AArch64InstructionSelector::tryOptSelect(MachineInstr &I) const {
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MachineIRBuilder MIB(I);
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MachineRegisterInfo &MRI = *MIB.getMRI();
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const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
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Register SrcReg1 = I.getOperand(2).getReg();
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Register SrcReg2 = I.getOperand(3).getReg();
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// We want to recognize this pattern:
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//
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// $z = G_FCMP pred, $x, $y
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@ -4218,37 +4298,8 @@ bool AArch64InstructionSelector::tryOptSelect(MachineInstr &I) const {
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}
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// Emit the select.
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// We may also be able to emit a CSINC if the RHS operand is a 1.
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const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg1, MRI, TRI);
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auto ValAndVReg =
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getConstantVRegValWithLookThrough(SrcReg2, MRI);
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if (SrcRB.getID() == AArch64::GPRRegBankID && ValAndVReg &&
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ValAndVReg->Value == 1) {
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unsigned Size = MRI.getType(SrcReg1).getSizeInBits();
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unsigned Opc = 0;
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Register Zero;
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if (Size == 64) {
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Opc = AArch64::CSINCXr;
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Zero = AArch64::XZR;
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} else {
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Opc = AArch64::CSINCWr;
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Zero = AArch64::WZR;
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}
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auto CSINC =
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MIB.buildInstr(Opc, {I.getOperand(0).getReg()}, {SrcReg1, Zero})
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.addImm(CondCode);
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constrainSelectedInstRegOperands(*CSINC, TII, TRI, RBI);
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I.eraseFromParent();
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return true;
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}
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unsigned CSelOpc = selectSelectOpc(I, MRI, RBI);
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auto CSel =
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MIB.buildInstr(CSelOpc, {I.getOperand(0).getReg()},
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{I.getOperand(2).getReg(), I.getOperand(3).getReg()})
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.addImm(CondCode);
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constrainSelectedInstRegOperands(*CSel, TII, TRI, RBI);
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emitSelect(I.getOperand(0).getReg(), I.getOperand(2).getReg(),
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I.getOperand(3).getReg(), CondCode, MIB);
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I.eraseFromParent();
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return true;
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}
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@ -45,10 +45,9 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 1, implicit $nzcv
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; CHECK: $w0 = COPY [[CSELWr]]
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
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; CHECK: $w0 = COPY [[CSINCWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = COPY $w1
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@ -77,10 +76,9 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: $wzr = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 1, implicit $nzcv
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; CHECK: $w0 = COPY [[CSELWr]]
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
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; CHECK: $w0 = COPY [[CSINCWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = COPY $w1
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@ -109,11 +107,10 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY1]], implicit-def $nzcv
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; CHECK: [[SUBSWrr1:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[SUBSWrr]], implicit-def $nzcv
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 11, implicit $nzcv
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; CHECK: $w0 = COPY [[CSELWr]]
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 10, implicit $nzcv
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; CHECK: $w0 = COPY [[CSINCWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = COPY $w1
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@ -142,11 +139,10 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY]], implicit-def $nzcv
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; CHECK: [[SUBSWrr1:%[0-9]+]]:gpr32 = SUBSWrr [[SUBSWrr]], [[COPY1]], implicit-def $nzcv
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; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 11, implicit $nzcv
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; CHECK: $w0 = COPY [[CSELWr]]
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 10, implicit $nzcv
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; CHECK: $w0 = COPY [[CSINCWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = COPY $w1
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@ -175,11 +171,9 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
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; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 1, implicit $nzcv
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; CHECK: $x0 = COPY [[CSELXr]]
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; CHECK: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 0, implicit $nzcv
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; CHECK: $x0 = COPY [[CSINCXr]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = COPY $x1
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@ -208,11 +202,9 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK: $xzr = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
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; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 1, implicit $nzcv
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; CHECK: $x0 = COPY [[CSELXr]]
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; CHECK: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 0, implicit $nzcv
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; CHECK: $x0 = COPY [[CSINCXr]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = COPY $x1
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@ -241,12 +233,10 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY1]], implicit-def $nzcv
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; CHECK: [[SUBSXrr1:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[SUBSXrr]], implicit-def $nzcv
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; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 11, implicit $nzcv
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; CHECK: $x0 = COPY [[CSELXr]]
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; CHECK: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 10, implicit $nzcv
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; CHECK: $x0 = COPY [[CSINCXr]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = COPY $x1
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@ -275,12 +265,10 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY]], implicit-def $nzcv
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; CHECK: [[SUBSXrr1:%[0-9]+]]:gpr64 = SUBSXrr [[SUBSXrr]], [[COPY1]], implicit-def $nzcv
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; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 11, implicit $nzcv
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; CHECK: $x0 = COPY [[CSELXr]]
|
||||
; CHECK: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 10, implicit $nzcv
|
||||
; CHECK: $x0 = COPY [[CSINCXr]]
|
||||
; CHECK: RET_ReallyLR implicit $x0
|
||||
%0:gpr(s64) = COPY $x0
|
||||
%1:gpr(s64) = COPY $x1
|
||||
@ -307,10 +295,9 @@ body: |
|
||||
; CHECK: liveins: $w0, $w1
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
|
||||
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
|
||||
; CHECK: [[ANDSWrr:%[0-9]+]]:gpr32 = ANDSWrr [[COPY1]], [[COPY]], implicit-def $nzcv
|
||||
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 0, implicit $nzcv
|
||||
; CHECK: $w0 = COPY [[CSELWr]]
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY1]], $wzr, 1, implicit $nzcv
|
||||
; CHECK: $w0 = COPY [[CSINCWr]]
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%0:gpr(s32) = COPY $w0
|
||||
%1:gpr(s32) = COPY $w1
|
||||
@ -338,11 +325,9 @@ body: |
|
||||
; CHECK: liveins: $x0, $x1
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr
|
||||
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
|
||||
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
|
||||
; CHECK: [[ANDSXrr:%[0-9]+]]:gpr64 = ANDSXrr [[COPY1]], [[COPY]], implicit-def $nzcv
|
||||
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY1]], 0, implicit $nzcv
|
||||
; CHECK: $x0 = COPY [[CSELXr]]
|
||||
; CHECK: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY1]], $xzr, 1, implicit $nzcv
|
||||
; CHECK: $x0 = COPY [[CSINCXr]]
|
||||
; CHECK: RET_ReallyLR implicit $x0
|
||||
%0:gpr(s64) = COPY $x0
|
||||
%1:gpr(s64) = COPY $x1
|
||||
@ -370,11 +355,10 @@ body: |
|
||||
; CHECK: liveins: $w0, $w1
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
|
||||
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
|
||||
; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]]
|
||||
; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ANDWrr]], 0, 0, implicit-def $nzcv
|
||||
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 8, implicit $nzcv
|
||||
; CHECK: $w0 = COPY [[CSELWr]]
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY1]], $wzr, 9, implicit $nzcv
|
||||
; CHECK: $w0 = COPY [[CSINCWr]]
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%0:gpr(s32) = COPY $w0
|
||||
%1:gpr(s32) = COPY $w1
|
||||
@ -402,11 +386,10 @@ body: |
|
||||
; CHECK: liveins: $w0, $w1
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
|
||||
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
|
||||
; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]]
|
||||
; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ANDWrr]], 42, 0, implicit-def $nzcv
|
||||
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 8, implicit $nzcv
|
||||
; CHECK: $w0 = COPY [[CSELWr]]
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY1]], $wzr, 9, implicit $nzcv
|
||||
; CHECK: $w0 = COPY [[CSINCWr]]
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%0:gpr(s32) = COPY $w0
|
||||
%1:gpr(s32) = COPY $w1
|
||||
@ -527,10 +510,8 @@ body: |
|
||||
; CHECK: liveins: $x0, $x1
|
||||
; CHECK: %copy:gpr64 = COPY $x1
|
||||
; CHECK: %zero:gpr64 = COPY $xzr
|
||||
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
|
||||
; CHECK: %one:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
|
||||
; CHECK: [[ANDSXrs:%[0-9]+]]:gpr64 = ANDSXrs %zero, %copy, 16, implicit-def $nzcv
|
||||
; CHECK: %select:gpr64 = CSELXr %one, %zero, 0, implicit $nzcv
|
||||
; CHECK: %select:gpr64 = CSINCXr %zero, $xzr, 1, implicit $nzcv
|
||||
; CHECK: $x0 = COPY %select
|
||||
; CHECK: RET_ReallyLR implicit $x0
|
||||
%copy:gpr(s64) = COPY $x1
|
||||
@ -561,9 +542,8 @@ body: |
|
||||
; CHECK: liveins: $w0, $w1
|
||||
; CHECK: %copy:gpr32 = COPY $w1
|
||||
; CHECK: %zero:gpr32 = COPY $wzr
|
||||
; CHECK: %one:gpr32 = MOVi32imm 1
|
||||
; CHECK: [[ANDSWrs:%[0-9]+]]:gpr32 = ANDSWrs %zero, %copy, 16, implicit-def $nzcv
|
||||
; CHECK: %select:gpr32 = CSELWr %one, %zero, 0, implicit $nzcv
|
||||
; CHECK: %select:gpr32 = CSINCWr %zero, $wzr, 1, implicit $nzcv
|
||||
; CHECK: $w0 = COPY %select
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%copy:gpr(s32) = COPY $w1
|
||||
|
||||
@ -64,3 +64,284 @@ body: |
|
||||
%4:fpr(s64) = G_SELECT %5(s1), %1, %2
|
||||
$d0 = COPY %4(s64)
|
||||
RET_ReallyLR implicit $d0
|
||||
...
|
||||
---
|
||||
name: csel
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $w0, $w1, $w2, $w3
|
||||
; CHECK-LABEL: name: csel
|
||||
; CHECK: liveins: $w0, $w1, $w2, $w3
|
||||
; CHECK: %reg0:gpr32 = COPY $w0
|
||||
; CHECK: %reg1:gpr32 = COPY $w1
|
||||
; CHECK: %t:gpr32 = COPY $w2
|
||||
; CHECK: %f:gpr32 = COPY $w3
|
||||
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
|
||||
; CHECK: %select:gpr32 = CSELWr %t, %f, 1, implicit $nzcv
|
||||
; CHECK: $w0 = COPY %select
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%reg0:gpr(s32) = COPY $w0
|
||||
%reg1:gpr(s32) = COPY $w1
|
||||
%cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
|
||||
%cond:gpr(s1) = G_TRUNC %cmp(s32)
|
||||
%t:gpr(s32) = COPY $w2
|
||||
%f:gpr(s32) = COPY $w3
|
||||
%select:gpr(s32) = G_SELECT %cond(s1), %t, %f
|
||||
$w0 = COPY %select(s32)
|
||||
RET_ReallyLR implicit $w0
|
||||
...
|
||||
---
|
||||
name: csinc_t_0_f_1
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $w0, $w1
|
||||
; G_SELECT cc, 0, 1 -> CSINC zreg, zreg, cc
|
||||
|
||||
; CHECK-LABEL: name: csinc_t_0_f_1
|
||||
; CHECK: liveins: $w0, $w1
|
||||
; CHECK: %reg0:gpr32 = COPY $w0
|
||||
; CHECK: %reg1:gpr32 = COPY $w1
|
||||
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
|
||||
; CHECK: %select:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
|
||||
; CHECK: $w0 = COPY %select
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%reg0:gpr(s32) = COPY $w0
|
||||
%reg1:gpr(s32) = COPY $w1
|
||||
%cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
|
||||
%cond:gpr(s1) = G_TRUNC %cmp(s32)
|
||||
%t:gpr(s32) = G_CONSTANT i32 0
|
||||
%f:gpr(s32) = G_CONSTANT i32 1
|
||||
%select:gpr(s32) = G_SELECT %cond(s1), %t, %f
|
||||
$w0 = COPY %select(s32)
|
||||
RET_ReallyLR implicit $w0
|
||||
...
|
||||
---
|
||||
name: csinv_t_0_f_neg_1
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $w0, $w1
|
||||
; G_SELECT cc 0, -1 -> CSINV zreg, zreg cc
|
||||
|
||||
; CHECK-LABEL: name: csinv_t_0_f_neg_1
|
||||
; CHECK: liveins: $w0, $w1
|
||||
; CHECK: %reg0:gpr32 = COPY $w0
|
||||
; CHECK: %reg1:gpr32 = COPY $w1
|
||||
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
|
||||
; CHECK: %select:gpr32 = CSINVWr $wzr, $wzr, 1, implicit $nzcv
|
||||
; CHECK: $w0 = COPY %select
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%reg0:gpr(s32) = COPY $w0
|
||||
%reg1:gpr(s32) = COPY $w1
|
||||
%cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
|
||||
%cond:gpr(s1) = G_TRUNC %cmp(s32)
|
||||
%t:gpr(s32) = G_CONSTANT i32 0
|
||||
%f:gpr(s32) = G_CONSTANT i32 -1
|
||||
%select:gpr(s32) = G_SELECT %cond(s1), %t, %f
|
||||
$w0 = COPY %select(s32)
|
||||
RET_ReallyLR implicit $w0
|
||||
...
|
||||
---
|
||||
name: csinc_t_1
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $w0, $w1, $w2
|
||||
; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
|
||||
|
||||
; CHECK-LABEL: name: csinc_t_1
|
||||
; CHECK: liveins: $w0, $w1, $w2
|
||||
; CHECK: %reg0:gpr32 = COPY $w0
|
||||
; CHECK: %reg1:gpr32 = COPY $w1
|
||||
; CHECK: %f:gpr32 = COPY $w2
|
||||
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
|
||||
; CHECK: %select:gpr32 = CSINCWr %f, $wzr, 0, implicit $nzcv
|
||||
; CHECK: $w0 = COPY %select
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%reg0:gpr(s32) = COPY $w0
|
||||
%reg1:gpr(s32) = COPY $w1
|
||||
%cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
|
||||
%cond:gpr(s1) = G_TRUNC %cmp(s32)
|
||||
%t:gpr(s32) = G_CONSTANT i32 1
|
||||
%f:gpr(s32) = COPY $w2
|
||||
%select:gpr(s32) = G_SELECT %cond(s1), %t, %f
|
||||
$w0 = COPY %select(s32)
|
||||
RET_ReallyLR implicit $w0
|
||||
...
|
||||
---
|
||||
name: csinv_t_neg_1
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $w0, $w1, $w2
|
||||
; G_SELECT cc, -1, f -> CSINV f, zreg, inv_cc
|
||||
|
||||
; CHECK-LABEL: name: csinv_t_neg_1
|
||||
; CHECK: liveins: $w0, $w1, $w2
|
||||
; CHECK: %reg0:gpr32 = COPY $w0
|
||||
; CHECK: %reg1:gpr32 = COPY $w1
|
||||
; CHECK: %f:gpr32 = COPY $w2
|
||||
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
|
||||
; CHECK: %select:gpr32 = CSINVWr %f, $wzr, 0, implicit $nzcv
|
||||
; CHECK: $w0 = COPY %select
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%reg0:gpr(s32) = COPY $w0
|
||||
%reg1:gpr(s32) = COPY $w1
|
||||
%cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
|
||||
%cond:gpr(s1) = G_TRUNC %cmp(s32)
|
||||
%t:gpr(s32) = G_CONSTANT i32 -1
|
||||
%f:gpr(s32) = COPY $w2
|
||||
%select:gpr(s32) = G_SELECT %cond(s1), %t, %f
|
||||
$w0 = COPY %select(s32)
|
||||
RET_ReallyLR implicit $w0
|
||||
...
|
||||
---
|
||||
name: csinc_f_1
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $w0, $w1, $w2
|
||||
; G_SELECT cc, t, 1 -> CSINC t, zreg, cc
|
||||
|
||||
; CHECK-LABEL: name: csinc_f_1
|
||||
; CHECK: liveins: $w0, $w1, $w2
|
||||
; CHECK: %reg0:gpr32 = COPY $w0
|
||||
; CHECK: %reg1:gpr32 = COPY $w1
|
||||
; CHECK: %t:gpr32 = COPY $w2
|
||||
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
|
||||
; CHECK: %select:gpr32 = CSINCWr %t, $wzr, 1, implicit $nzcv
|
||||
; CHECK: $w0 = COPY %select
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%reg0:gpr(s32) = COPY $w0
|
||||
%reg1:gpr(s32) = COPY $w1
|
||||
%cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
|
||||
%cond:gpr(s1) = G_TRUNC %cmp(s32)
|
||||
%t:gpr(s32) = COPY $w2
|
||||
%f:gpr(s32) = G_CONSTANT i32 1
|
||||
%select:gpr(s32) = G_SELECT %cond(s1), %t, %f
|
||||
$w0 = COPY %select(s32)
|
||||
RET_ReallyLR implicit $w0
|
||||
...
|
||||
---
|
||||
name: csinc_f_neg_1
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $w0, $w1, $w2
|
||||
; G_SELECT cc, t, -1 -> CSINC t, zreg, cc
|
||||
|
||||
; CHECK-LABEL: name: csinc_f_neg_1
|
||||
; CHECK: liveins: $w0, $w1, $w2
|
||||
; CHECK: %reg0:gpr32 = COPY $w0
|
||||
; CHECK: %reg1:gpr32 = COPY $w1
|
||||
; CHECK: %t:gpr32 = COPY $w2
|
||||
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
|
||||
; CHECK: %select:gpr32 = CSINVWr %t, $wzr, 1, implicit $nzcv
|
||||
; CHECK: $w0 = COPY %select
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%reg0:gpr(s32) = COPY $w0
|
||||
%reg1:gpr(s32) = COPY $w1
|
||||
%cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1
|
||||
%cond:gpr(s1) = G_TRUNC %cmp(s32)
|
||||
%t:gpr(s32) = COPY $w2
|
||||
%f:gpr(s32) = G_CONSTANT i32 -1
|
||||
%select:gpr(s32) = G_SELECT %cond(s1), %t, %f
|
||||
$w0 = COPY %select(s32)
|
||||
RET_ReallyLR implicit $w0
|
||||
...
|
||||
---
|
||||
name: csinc_t_1_no_cmp
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $w0, $w1
|
||||
; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
|
||||
|
||||
; CHECK-LABEL: name: csinc_t_1_no_cmp
|
||||
; CHECK: liveins: $w0, $w1
|
||||
; CHECK: %reg0:gpr32 = COPY $w0
|
||||
; CHECK: %f:gpr32 = COPY $w1
|
||||
; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
|
||||
; CHECK: %select:gpr32 = CSINCWr %f, $wzr, 0, implicit $nzcv
|
||||
; CHECK: $w0 = COPY %select
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%reg0:gpr(s32) = COPY $w0
|
||||
%cond:gpr(s1) = G_TRUNC %reg0(s32)
|
||||
%t:gpr(s32) = G_CONSTANT i32 1
|
||||
%f:gpr(s32) = COPY $w1
|
||||
%select:gpr(s32) = G_SELECT %cond(s1), %t, %f
|
||||
$w0 = COPY %select(s32)
|
||||
RET_ReallyLR implicit $w0
|
||||
|
||||
...
|
||||
---
|
||||
name: csinc_f_1_no_cmp
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $w0, $w1
|
||||
; G_SELECT cc, t, 1 -> CSINC t, zreg, cc
|
||||
|
||||
; CHECK-LABEL: name: csinc_f_1_no_cmp
|
||||
; CHECK: liveins: $w0, $w1
|
||||
; CHECK: %reg0:gpr32 = COPY $w0
|
||||
; CHECK: %t:gpr32 = COPY $w1
|
||||
; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
|
||||
; CHECK: %select:gpr32 = CSINCWr %t, $wzr, 1, implicit $nzcv
|
||||
; CHECK: $w0 = COPY %select
|
||||
; CHECK: RET_ReallyLR implicit $w0
|
||||
%reg0:gpr(s32) = COPY $w0
|
||||
%cond:gpr(s1) = G_TRUNC %reg0(s32)
|
||||
%t:gpr(s32) = COPY $w1
|
||||
%f:gpr(s32) = G_CONSTANT i32 1
|
||||
%select:gpr(s32) = G_SELECT %cond(s1), %t, %f
|
||||
$w0 = COPY %select(s32)
|
||||
RET_ReallyLR implicit $w0
|
||||
|
||||
...
|
||||
---
|
||||
name: csinc_t_1_no_cmp_s64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $x0, $x1
|
||||
; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
|
||||
|
||||
; CHECK-LABEL: name: csinc_t_1_no_cmp_s64
|
||||
; CHECK: liveins: $x0, $x1
|
||||
; CHECK: %reg0:gpr64 = COPY $x0
|
||||
; CHECK: %cond:gpr32 = COPY %reg0.sub_32
|
||||
; CHECK: %f:gpr64 = COPY $x1
|
||||
; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv
|
||||
; CHECK: %select:gpr64 = CSINCXr %f, $xzr, 0, implicit $nzcv
|
||||
; CHECK: $x0 = COPY %select
|
||||
; CHECK: RET_ReallyLR implicit $x0
|
||||
%reg0:gpr(s64) = COPY $x0
|
||||
%cond:gpr(s1) = G_TRUNC %reg0(s64)
|
||||
%t:gpr(s64) = G_CONSTANT i64 1
|
||||
%f:gpr(s64) = COPY $x1
|
||||
%select:gpr(s64) = G_SELECT %cond(s1), %t, %f
|
||||
$x0 = COPY %select(s64)
|
||||
RET_ReallyLR implicit $x0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user