[10/11][Clang][RISCV] Expand all variants for vget on tuple types

This is the 10th patch of the patch-set. For the cover letter, please
checkout D152069.

Depends on D152077.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D152078

clang/include/clang/Basic/riscv_vector.td

@@ -2629,11 +2629,10 @@ let HasMasked = false, HasVL = false, IRName = "" in {
       def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "csilxfd", dst_lmul # "v">;
       def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "UvUvKz", "csil", dst_lmul # "Uv">;
     }
-    foreach nf = [2] in {
-      let Log2LMUL = [0] in {
-        defvar T = "(Tuple:" # nf # ")";
-        def : RVVBuiltin<T # "vv", "v" # T # "vKz", "i", "v">;
-      }
+    foreach nf = NFList in {
+      defvar T = "(Tuple:" # nf # ")";
+      def : RVVBuiltin<T # "vv", "v" # T # "vKz", "csilxfd", "v">;
+      def : RVVBuiltin<T # "UvUv", "Uv" # T # "UvKz", "csil", "Uv">;
     }
   }
 

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget_tuple.c

@@ -1,20 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
-// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
-// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
-// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
-// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
-
-#include <riscv_vector.h>
-
-// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vget_v_i32m1x2_i32m1
-// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC_COERCE0:%.*]], <vscale x 2 x i32> [[SRC_COERCE1:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> [[SRC_COERCE0]], 0
-// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], <vscale x 2 x i32> [[SRC_COERCE1]], 1
-// CHECK-RV64-NEXT:    [[TMP2:%.*]] = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP1]], 0
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP2]]
-//
-vint32m1_t test_vget_v_i32m1x2_i32m1(vint32m1x2_t src) {
-  return __riscv_vget_v_i32m1x2_i32m1(src, 0);
-}