diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ext.mir new file mode 100644 index 000000000000..a98324ea00ac --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ext.mir @@ -0,0 +1,49 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ +# RUN: | FileCheck %s +--- +name: sext_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: sext_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[ADD]](s32) + ; CHECK-NEXT: $x10 = COPY [[SEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_ADD %2, %3 + %5:_(s64) = G_SEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +... +--- +name: zext_i32 +body: | + bb.0.entry: + ; CHECK-LABEL: name: zext_i32 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]] + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ADD]](s32) + ; CHECK-NEXT: $x10 = COPY [[ZEXT]](s64) + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:_(s64) = COPY $x10 + %1:_(s64) = COPY $x11 + %2:_(s32) = G_TRUNC %0(s64) + %3:_(s32) = G_TRUNC %1(s64) + %4:_(s32) = G_ADD %2, %3 + %5:_(s64) = G_ZEXT %4(s32) + $x10 = COPY %5(s64) + PseudoRET implicit $x10 + +...