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[AMDGPU] Do not reassign spilled registers
We cannot call LRM::unassign() if LRM::assign() was never called before, these are symmetrical calls. There are two ways of assigning a physical register to virtual, via LRM::assign() and via VRM::assignVirt2Phys(). LRM::assign() will call the VRM to assign the register and then update LiveIntervalUnion. Inline spiller calls VRM directly and thus LiveIntervalUnion never gets updated. A call to LRM::unassign() then asserts about inconsistent liveness. We have to note that not all callers of the InlineSpiller even have LRM to pass, RegAllocPBQP does not have it, so we cannot always pass LRM into the spiller. The only way to get into that spiller LRE_DidCloneVirtReg() call is from LiveRangeEdit::eliminateDeadDefs if we split an LI. This patch refuses to reassign a LiveInterval created by a split to workaround the problem. In fact we cannot reassign a spill anyway as all registers of the needed class are occupied and we are spilling. Fixes: SWDEV-267996 Differential Revision: https://reviews.llvm.org/D95489
This commit is contained in:
Stanislav Mekhanoshin
parent
6612c2bb68
commit
d91ee2f782
@ -190,6 +190,14 @@ GCNNSAReassign::CheckNSA(const MachineInstr &MI, bool Fast) const {
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if (MRI->getRegClass(Reg) != &AMDGPU::VGPR_32RegClass || Op.getSubReg())
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return NSA_Status::FIXED;
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// InlineSpiller does not call LRM::assign() after an LI split leaving
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// it in an inconsistent state, so we cannot call LRM::unassign().
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// See llvm bug #48911.
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// Skip reassign if a register has originated from such split.
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// FIXME: Remove the workaround when bug #48911 is fixed.
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if (VRM->getPreSplitReg(Reg))
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return NSA_Status::FIXED;
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const MachineInstr *Def = MRI->getUniqueVRegDef(Reg);
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if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg)
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@ -471,6 +471,14 @@ bool GCNRegBankReassign::isReassignable(Register Reg) const {
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if (Reg.isPhysical() || !VRM->isAssignedReg(Reg))
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return false;
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// InlineSpiller does not call LRM::assign() after an LI split leaving it
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// in an inconsistent state, so we cannot call LRM::unassign().
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// See llvm bug #48911.
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// Skip reassign if a register has originated from such split.
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// FIXME: Remove the workaround when bug #48911 is fixed.
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if (VRM->getPreSplitReg(Reg))
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return false;
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const MachineInstr *Def = MRI->getUniqueVRegDef(Reg);
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Register PhysReg = VRM->getPhys(Reg);
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72
llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
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72
llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
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@ -0,0 +1,72 @@
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass greedy,amdgpu-nsa-reassign,virtregrewriter,si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
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--- |
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define amdgpu_kernel void @nsa_reassign() #0 { ret void }
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define amdgpu_kernel void @do_not_reassign_spill() #0 { ret void }
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attributes #0 = { "amdgpu-num-vgpr"="8" }
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...
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# GCN-LABEL: name: nsa_reassign
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# GCN: IMAGE_SAMPLE_C_L_V1_V8_gfx10
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---
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name: nsa_reassign
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tracksRegLiveness: true
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machineFunctionInfo:
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stackPtrOffsetReg: $sgpr32
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stack:
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- { id: 0, type: default, offset: 0, size: 4, alignment: 4 }
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
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- { id: 1, class: vgpr_32, preferred-register: '$vgpr1' }
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- { id: 2, class: vgpr_32, preferred-register: '$vgpr2' }
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- { id: 3, class: vgpr_32, preferred-register: '$vgpr3' }
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- { id: 4, class: vgpr_32, preferred-register: '$vgpr4' }
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- { id: 5, class: vgpr_32, preferred-register: '$vgpr5' }
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- { id: 6, class: vgpr_32, preferred-register: '$vgpr6' }
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- { id: 7, class: vgpr_32, preferred-register: '$vgpr7' }
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body: |
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bb.0:
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%0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%1 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%2 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%3 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%4 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%5 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%6 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%7:vgpr_32 = IMAGE_SAMPLE_C_L_V1_V5_nsa_gfx10 %0, %2, %4, %5, %6, undef $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, undef $sgpr8_sgpr9_sgpr10_sgpr11, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "ImageResource")
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S_ENDPGM 0, implicit %7
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...
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# GCN-LABEL: do_not_reassign_spill
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# GCN: IMAGE_SAMPLE_C_L_V1_V5_nsa_gfx10
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---
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name: do_not_reassign_spill
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tracksRegLiveness: true
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machineFunctionInfo:
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stackPtrOffsetReg: $sgpr32
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stack:
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- { id: 0, type: default, offset: 0, size: 4, alignment: 4 }
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
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- { id: 1, class: vgpr_32, preferred-register: '$vgpr1' }
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- { id: 2, class: vgpr_32, preferred-register: '$vgpr2' }
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- { id: 3, class: vgpr_32, preferred-register: '$vgpr3' }
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- { id: 4, class: vgpr_32, preferred-register: '$vgpr4' }
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- { id: 5, class: vgpr_32, preferred-register: '$vgpr5' }
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- { id: 6, class: vgpr_32, preferred-register: '$vgpr6' }
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- { id: 7, class: vgpr_32, preferred-register: '$vgpr7' }
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body: |
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bb.0:
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%0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%1 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%2 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%3 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%4 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%5 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%6 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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S_NOP 0, implicit-def dead $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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S_NOP 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5, implicit %6
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%7:vgpr_32 = IMAGE_SAMPLE_C_L_V1_V5_nsa_gfx10 %0, %2, %4, %5, %6, undef $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, undef $sgpr8_sgpr9_sgpr10_sgpr11, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from custom "ImageResource")
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S_ENDPGM 0, implicit %7
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...
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38
llvm/test/CodeGen/AMDGPU/regbank-reassign-split.mir
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38
llvm/test/CodeGen/AMDGPU/regbank-reassign-split.mir
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@ -0,0 +1,38 @@
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass greedy,amdgpu-regbanks-reassign,virtregrewriter -o - %s | FileCheck -check-prefix=GCN %s
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--- |
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define amdgpu_kernel void @do_not_reassign_spill() #0 { ret void }
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attributes #0 = { "amdgpu-num-vgpr"="8" }
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...
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# GCN-LABEL: do_not_reassign_spill{{$}}
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# GCN: V_AND_B32_e32 killed $vgpr1, killed $vgpr5,
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---
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name: do_not_reassign_spill
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tracksRegLiveness: true
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machineFunctionInfo:
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stackPtrOffsetReg: $sgpr32
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stack:
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- { id: 0, type: default, offset: 0, size: 4, alignment: 4 }
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
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- { id: 1, class: vgpr_32, preferred-register: '$vgpr1' }
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- { id: 2, class: vgpr_32, preferred-register: '$vgpr2' }
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- { id: 3, class: vgpr_32, preferred-register: '$vgpr3' }
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- { id: 4, class: vgpr_32, preferred-register: '$vgpr4' }
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- { id: 5, class: vgpr_32, preferred-register: '$vgpr5' }
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- { id: 6, class: vgpr_32 }
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body: |
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bb.0:
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%0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%1 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%2 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%3 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%4 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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%5 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, align 4, addrspace 5)
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S_NOP 0, implicit-def dead $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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S_NOP 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5
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%6 = V_AND_B32_e32 %1, %5, implicit $exec
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S_ENDPGM 0, implicit %6
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...
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