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[NFC][Clang][RISCV] Fix typos of riscv-v-spec doc in riscv_vector.td (#65944)
Fix index typos, s.t. indexes in comments be same with riscv-v-spec v1.0 doc.
This commit is contained in:
Ying Chen
GitHub
parent
0323938d3c
commit
d9c9c9f2d9
@ -1601,8 +1601,8 @@ defm : RVVIndexedSegStoreTuple<"vsuxseg">;
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defm : RVVIndexedSegStoreTuple<"vsoxseg">;
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}
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// 12. Vector Integer Arithmetic Instructions
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// 12.1. Vector Single-Width Integer Add and Subtract
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// 11. Vector Integer Arithmetic Instructions
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// 11.1. Vector Single-Width Integer Add and Subtract
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let UnMaskedPolicyScheme = HasPassthruOperand in {
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defm vadd : RVVIntBinBuiltinSet;
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defm vsub : RVVIntBinBuiltinSet;
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@ -1612,7 +1612,7 @@ defm vrsub : RVVOutOp1BuiltinSet<"vrsub", "csil",
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}
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defm vneg_v : RVVPseudoUnaryBuiltin<"vrsub", "csil">;
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// 12.2. Vector Widening Integer Add/Subtract
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// 11.2. Vector Widening Integer Add/Subtract
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// Widening unsigned integer add/subtract, 2*SEW = SEW +/- SEW
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let UnMaskedPolicyScheme = HasPassthruOperand in {
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defm vwaddu : RVVUnsignedWidenBinBuiltinSet;
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@ -1632,7 +1632,7 @@ defm vwcvtu_x_x_v : RVVPseudoVWCVTBuiltin<"vwaddu", "vwcvtu_x", "csi",
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defm vwcvt_x_x_v : RVVPseudoVWCVTBuiltin<"vwadd", "vwcvt_x", "csi",
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[["w", "wv"]]>;
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// 12.3. Vector Integer Extension
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// 11.3. Vector Integer Extension
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let UnMaskedPolicyScheme = HasPassthruOperand in {
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let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
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def vsext_vf2 : RVVIntExt<"vsext", "w", "wv", "csi">;
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@ -1648,7 +1648,7 @@ let Log2LMUL = [-3, -2, -1, 0] in {
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}
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}
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// 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
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// 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
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let HasMasked = false, MaskedPolicyScheme = NonePolicy in {
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let UnMaskedPolicyScheme = HasPassthruOperand in {
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defm vadc : RVVCarryinBuiltinSet;
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@ -1660,7 +1660,7 @@ let HasMasked = false, MaskedPolicyScheme = NonePolicy in {
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defm vmsbc : RVVIntMaskOutBuiltinSet;
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}
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// 12.5. Vector Bitwise Logical Instructions
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// 11.5. Vector Bitwise Logical Instructions
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let UnMaskedPolicyScheme = HasPassthruOperand in {
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defm vand : RVVIntBinBuiltinSet;
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defm vxor : RVVIntBinBuiltinSet;
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@ -1668,13 +1668,13 @@ defm vor : RVVIntBinBuiltinSet;
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}
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defm vnot_v : RVVPseudoVNotBuiltin<"vxor", "csil">;
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// 12.6. Vector Single-Width Bit Shift Instructions
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// 11.6. Vector Single-Width Shift Instructions
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let UnMaskedPolicyScheme = HasPassthruOperand in {
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defm vsll : RVVShiftBuiltinSet;
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defm vsrl : RVVUnsignedShiftBuiltinSet;
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defm vsra : RVVSignedShiftBuiltinSet;
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// 12.7. Vector Narrowing Integer Right Shift Instructions
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// 11.7. Vector Narrowing Integer Right Shift Instructions
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defm vnsrl : RVVUnsignedNShiftBuiltinSet;
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defm vnsra : RVVSignedNShiftBuiltinSet;
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}
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@ -1682,7 +1682,7 @@ defm vncvt_x_x_w : RVVPseudoVNCVTBuiltin<"vnsrl", "vncvt_x", "csi",
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[["v", "vw"],
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["Uv", "UvUw"]]>;
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// 12.8. Vector Integer Comparison Instructions
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// 11.8. Vector Integer Compare Instructions
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let MaskedPolicyScheme = HasPassthruOperand,
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HasTailPolicy = false in {
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defm vmseq : RVVIntMaskOutBuiltinSet;
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@ -1697,14 +1697,14 @@ defm vmsgeu : RVVUnsignedMaskOutBuiltinSet;
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defm vmsge : RVVSignedMaskOutBuiltinSet;
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}
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// 12.9. Vector Integer Min/Max Instructions
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// 11.9. Vector Integer Min/Max Instructions
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let UnMaskedPolicyScheme = HasPassthruOperand in {
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defm vminu : RVVUnsignedBinBuiltinSet;
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defm vmin : RVVSignedBinBuiltinSet;
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defm vmaxu : RVVUnsignedBinBuiltinSet;
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defm vmax : RVVSignedBinBuiltinSet;
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// 12.10. Vector Single-Width Integer Multiply Instructions
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// 11.10. Vector Single-Width Integer Multiply Instructions
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defm vmul : RVVIntBinBuiltinSet;
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defm vmulh : RVVSignedBinBuiltinSet;
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defm vmulhu : RVVUnsignedBinBuiltinSet;
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@ -1712,14 +1712,14 @@ defm vmulhsu : RVVOutOp1BuiltinSet<"vmulhsu", "csil",
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[["vv", "v", "vvUv"],
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["vx", "v", "vvUe"]]>;
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// 12.11. Vector Integer Divide Instructions
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// 11.11. Vector Integer Divide Instructions
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defm vdivu : RVVUnsignedBinBuiltinSet;
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defm vdiv : RVVSignedBinBuiltinSet;
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defm vremu : RVVUnsignedBinBuiltinSet;
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defm vrem : RVVSignedBinBuiltinSet;
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}
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// 12.12. Vector Widening Integer Multiply Instructions
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// 11.12. Vector Widening Integer Multiply Instructions
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let Log2LMUL = [-3, -2, -1, 0, 1, 2], UnMaskedPolicyScheme = HasPassthruOperand in {
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defm vwmul : RVVOutOp0Op1BuiltinSet<"vwmul", "csi",
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[["vv", "w", "wvv"],
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@ -1732,14 +1732,14 @@ defm vwmulsu : RVVOutOp0Op1BuiltinSet<"vwmulsu", "csi",
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["vx", "w", "wvUe"]]>;
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}
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// 12.13. Vector Single-Width Integer Multiply-Add Instructions
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// 11.13. Vector Single-Width Integer Multiply-Add Instructions
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let UnMaskedPolicyScheme = HasPolicyOperand in {
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defm vmacc : RVVIntTerBuiltinSet;
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defm vnmsac : RVVIntTerBuiltinSet;
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defm vmadd : RVVIntTerBuiltinSet;
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defm vnmsub : RVVIntTerBuiltinSet;
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// 12.14. Vector Widening Integer Multiply-Add Instructions
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// 11.14. Vector Widening Integer Multiply-Add Instructions
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let HasMaskedOffOperand = false,
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Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
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defm vwmaccu : RVVOutOp1Op2BuiltinSet<"vwmaccu", "csi",
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@ -1756,7 +1756,7 @@ defm vwmaccus : RVVOutOp1Op2BuiltinSet<"vwmaccus", "csi",
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}
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}
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// 12.15. Vector Integer Merge Instructions
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// 11.15. Vector Integer Merge Instructions
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// C/C++ Operand: (mask, op1, op2, vl), Intrinsic: (passthru, op1, op2, mask, vl)
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let HasMasked = false,
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UnMaskedPolicyScheme = HasPassthruOperand,
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@ -1774,7 +1774,7 @@ let HasMasked = false,
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["vxm", "Uv", "UvUvUem"]]>;
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}
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// 12.16. Vector Integer Move Instructions
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// 11.16. Vector Integer Move Instructions
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let HasMasked = false,
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UnMaskedPolicyScheme = HasPassthruOperand,
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MaskedPolicyScheme = NonePolicy,
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@ -1792,7 +1792,7 @@ let HasMasked = false,
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["x", "Uv", "UvUe"]]>;
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}
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// 13. Vector Fixed-Point Arithmetic Instructions
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// 12. Vector Fixed-Point Arithmetic Instructions
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let HeaderCode =
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[{
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enum __RISCV_VXRM {
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@ -1804,7 +1804,7 @@ enum __RISCV_VXRM {
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}] in
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def vxrm_enum : RVVHeader;
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// 13.1. Vector Single-Width Saturating Add and Subtract
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// 12.1. Vector Single-Width Saturating Add and Subtract
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let UnMaskedPolicyScheme = HasPassthruOperand in {
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defm vsaddu : RVVUnsignedBinBuiltinSet;
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defm vsadd : RVVSignedBinBuiltinSet;
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@ -1846,16 +1846,16 @@ let ManualCodegen = [{
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return Builder.CreateCall(F, Operands, "");
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}
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}] in {
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// 13.2. Vector Single-Width Averaging Add and Subtract
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// 12.2. Vector Single-Width Averaging Add and Subtract
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defm vaaddu : RVVUnsignedBinBuiltinSetRoundingMode;
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defm vaadd : RVVSignedBinBuiltinSetRoundingMode;
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defm vasubu : RVVUnsignedBinBuiltinSetRoundingMode;
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defm vasub : RVVSignedBinBuiltinSetRoundingMode;
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// 13.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
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// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
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defm vsmul : RVVSignedBinBuiltinSetRoundingMode;
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// 13.4. Vector Single-Width Scaling Shift Instructions
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// 12.4. Vector Single-Width Scaling Shift Instructions
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defm vssrl : RVVUnsignedShiftBuiltinSetRoundingMode;
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defm vssra : RVVSignedShiftBuiltinSetRoundingMode;
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}
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@ -1896,13 +1896,13 @@ let ManualCodegen = [{
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return Builder.CreateCall(F, Operands, "");
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}
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}] in {
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// 13.5. Vector Narrowing Fixed-Point Clip Instructions
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// 12.5. Vector Narrowing Fixed-Point Clip Instructions
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defm vnclipu : RVVUnsignedNShiftBuiltinSetRoundingMode;
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defm vnclip : RVVSignedNShiftBuiltinSetRoundingMode;
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}
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}
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// 14. Vector Floating-Point Instructions
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// 13. Vector Floating-Point Instructions
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let HeaderCode =
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[{
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enum __RISCV_FRM {
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@ -1961,32 +1961,32 @@ let ManualCodegen = [{
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}
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}] in {
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let HasFRMRoundModeOp = true in {
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// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
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// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
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defm vfadd : RVVFloatingBinBuiltinSetRoundingMode;
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defm vfsub : RVVFloatingBinBuiltinSetRoundingMode;
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defm vfrsub : RVVFloatingBinVFBuiltinSetRoundingMode;
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// 14.3. Vector Widening Floating-Point Add/Subtract Instructions
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// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
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// Widening FP add/subtract, 2*SEW = 2*SEW +/- SEW
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defm vfwadd : RVVFloatingWidenOp0BinBuiltinSetRoundingMode;
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defm vfwsub : RVVFloatingWidenOp0BinBuiltinSetRoundingMode;
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// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
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// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
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defm vfmul : RVVFloatingBinBuiltinSetRoundingMode;
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defm vfdiv : RVVFloatingBinBuiltinSetRoundingMode;
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defm vfrdiv : RVVFloatingBinVFBuiltinSetRoundingMode;
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}
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// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
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// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
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defm vfadd : RVVFloatingBinBuiltinSet;
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defm vfsub : RVVFloatingBinBuiltinSet;
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defm vfrsub : RVVFloatingBinVFBuiltinSet;
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// 14.3. Vector Widening Floating-Point Add/Subtract Instructions
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// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
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// Widening FP add/subtract, 2*SEW = 2*SEW +/- SEW
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defm vfwadd : RVVFloatingWidenOp0BinBuiltinSet;
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defm vfwsub : RVVFloatingWidenOp0BinBuiltinSet;
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// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
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// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
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defm vfmul : RVVFloatingBinBuiltinSet;
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defm vfdiv : RVVFloatingBinBuiltinSet;
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defm vfrdiv : RVVFloatingBinVFBuiltinSet;
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@ -2038,24 +2038,24 @@ let ManualCodegen = [{
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}
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}] in {
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let HasFRMRoundModeOp = true in {
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// 14.3. Vector Widening Floating-Point Add/Subtract Instructions
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// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
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// Widening FP add/subtract, 2*SEW = SEW +/- SEW
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defm vfwadd : RVVFloatingWidenBinBuiltinSetRoundingMode;
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defm vfwsub : RVVFloatingWidenBinBuiltinSetRoundingMode;
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// 14.5. Vector Widening Floating-Point Multiply
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// 13.5. Vector Widening Floating-Point Multiply
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let Log2LMUL = [-2, -1, 0, 1, 2] in {
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defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "xf",
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[["vv", "w", "wvvu"],
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["vf", "w", "wveu"]]>;
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}
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}
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// 14.3. Vector Widening Floating-Point Add/Subtract Instructions
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// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
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// Widening FP add/subtract, 2*SEW = SEW +/- SEW
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defm vfwadd : RVVFloatingWidenBinBuiltinSet;
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defm vfwsub : RVVFloatingWidenBinBuiltinSet;
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// 14.5. Vector Widening Floating-Point Multiply
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// 13.5. Vector Widening Floating-Point Multiply
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let Log2LMUL = [-2, -1, 0, 1, 2] in {
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defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "xf",
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[["vv", "w", "wvv"],
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@ -2104,7 +2104,7 @@ let ManualCodegen = [{
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}
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}] in {
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let HasFRMRoundModeOp = 1 in {
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// 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
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// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
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defm vfmacc : RVVFloatingTerBuiltinSetRoundingMode;
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defm vfnmacc : RVVFloatingTerBuiltinSetRoundingMode;
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defm vfmsac : RVVFloatingTerBuiltinSetRoundingMode;
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@ -2114,7 +2114,7 @@ let ManualCodegen = [{
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defm vfmsub : RVVFloatingTerBuiltinSetRoundingMode;
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defm vfnmsub : RVVFloatingTerBuiltinSetRoundingMode;
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}
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// 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
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// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
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defm vfmacc : RVVFloatingTerBuiltinSet;
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defm vfnmacc : RVVFloatingTerBuiltinSet;
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defm vfmsac : RVVFloatingTerBuiltinSet;
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@ -2163,13 +2163,13 @@ let ManualCodegen = [{
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}
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}] in {
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let HasFRMRoundModeOp = 1 in {
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// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
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// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
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defm vfwmacc : RVVFloatingWidenTerBuiltinSetRoundingMode;
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defm vfwnmacc : RVVFloatingWidenTerBuiltinSetRoundingMode;
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defm vfwmsac : RVVFloatingWidenTerBuiltinSetRoundingMode;
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defm vfwnmsac : RVVFloatingWidenTerBuiltinSetRoundingMode;
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}
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// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
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// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
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defm vfwmacc : RVVFloatingWidenTerBuiltinSet;
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defm vfwnmacc : RVVFloatingWidenTerBuiltinSet;
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defm vfwmsac : RVVFloatingWidenTerBuiltinSet;
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@ -2223,27 +2223,27 @@ let ManualCodegen = [{
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}
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}] in {
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let HasFRMRoundModeOp = 1 in {
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// 14.8. Vector Floating-Point Square-Root Instruction
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// 13.8. Vector Floating-Point Square-Root Instruction
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defm vfsqrt : RVVOutBuiltinSet<"vfsqrt", "xfd", [["v", "v", "vvu"]]>;
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// 14.10. Vector Floating-Point Reciprocal Estimate Instruction
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// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
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defm vfrec7 : RVVOutBuiltinSet<"vfrec7", "xfd", [["v", "v", "vvu"]]>;
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}
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// 14.8. Vector Floating-Point Square-Root Instruction
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// 13.8. Vector Floating-Point Square-Root Instruction
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defm vfsqrt : RVVOutBuiltinSet<"vfsqrt", "xfd", [["v", "v", "vv"]]>;
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// 14.10. Vector Floating-Point Reciprocal Estimate Instruction
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// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
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defm vfrec7 : RVVOutBuiltinSet<"vfrec7", "xfd", [["v", "v", "vv"]]>;
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}
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// 14.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
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// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
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def vfrsqrt7 : RVVFloatingUnaryVVBuiltin;
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// 14.11. Vector Floating-Point MIN/MAX Instructions
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// 13.11. Vector Floating-Point MIN/MAX Instructions
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defm vfmin : RVVFloatingBinBuiltinSet;
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defm vfmax : RVVFloatingBinBuiltinSet;
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// 14.12. Vector Floating-Point Sign-Injection Instructions
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// 13.12. Vector Floating-Point Sign-Injection Instructions
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defm vfsgnj : RVVFloatingBinBuiltinSet;
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defm vfsgnjn : RVVFloatingBinBuiltinSet;
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defm vfsgnjx : RVVFloatingBinBuiltinSet;
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@ -2251,7 +2251,7 @@ defm vfsgnjx : RVVFloatingBinBuiltinSet;
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defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "xfd">;
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defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "xfd">;
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// 14.13. Vector Floating-Point Compare Instructions
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// 13.13. Vector Floating-Point Compare Instructions
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let MaskedPolicyScheme = HasPassthruOperand,
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HasTailPolicy = false in {
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defm vmfeq : RVVFloatingMaskOutBuiltinSet;
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@ -2262,11 +2262,11 @@ defm vmfgt : RVVFloatingMaskOutBuiltinSet;
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defm vmfge : RVVFloatingMaskOutBuiltinSet;
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}
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// 14.14. Vector Floating-Point Classify Instruction
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// 13.14. Vector Floating-Point Classify Instruction
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let Name = "vfclass_v", UnMaskedPolicyScheme = HasPassthruOperand in
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def vfclass : RVVOp0Builtin<"Uv", "Uvv", "xfd">;
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// 14.15. Vector Floating-Point Merge Instructio
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// 13.15. Vector Floating-Point Merge Instruction
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// C/C++ Operand: (mask, op1, op2, vl), Builtin: (op1, op2, mask, vl)
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let HasMasked = false,
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UnMaskedPolicyScheme = HasPassthruOperand,
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@ -2286,7 +2286,7 @@ let HasMasked = false,
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[["vfm", "v", "vvem"]]>;
|
||||
}
|
||||
|
||||
// 14.16. Vector Floating-Point Move Instruction
|
||||
// 13.16. Vector Floating-Point Move Instruction
|
||||
let HasMasked = false,
|
||||
UnMaskedPolicyScheme = HasPassthruOperand,
|
||||
SupportOverloading = false,
|
||||
@ -2295,12 +2295,12 @@ let HasMasked = false,
|
||||
defm vfmv_v : RVVOutBuiltinSet<"vfmv_v_f", "xfd",
|
||||
[["f", "v", "ve"]]>;
|
||||
|
||||
// 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions
|
||||
// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
|
||||
let UnMaskedPolicyScheme = HasPassthruOperand in {
|
||||
def vfcvt_rtz_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_rtz_xu">;
|
||||
def vfcvt_rtz_x_f_v : RVVConvToSignedBuiltin<"vfcvt_rtz_x">;
|
||||
|
||||
// 14.18. Widening Floating-Point/Integer Type-Convert Instructions
|
||||
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
|
||||
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
|
||||
def vfwcvt_rtz_xu_f_v : RVVConvToWidenUnsignedBuiltin<"vfwcvt_rtz_xu">;
|
||||
def vfwcvt_rtz_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_rtz_x">;
|
||||
@ -2315,7 +2315,7 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
|
||||
}
|
||||
}
|
||||
|
||||
// 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
|
||||
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
|
||||
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
|
||||
def vfncvt_rtz_xu_f_w : RVVConvToNarrowingUnsignedBuiltin<"vfncvt_rtz_xu">;
|
||||
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
|
||||
@ -2379,7 +2379,7 @@ let ManualCodegen = [{
|
||||
RVVConvBuiltinSet<"vfcvt_f_xu_v", "sil", [["Fv", "FvUvu"]]>;
|
||||
}
|
||||
|
||||
// 14.18. Widening Floating-Point/Integer Type-Convert Instructions
|
||||
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
|
||||
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
|
||||
let OverloadedName = "vfwcvt_x" in
|
||||
defm :
|
||||
@ -2388,7 +2388,7 @@ let ManualCodegen = [{
|
||||
defm :
|
||||
RVVConvBuiltinSet<"vfwcvt_xu_f_v", "xf", [["Uw", "Uwvu"]]>;
|
||||
}
|
||||
// 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
|
||||
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
|
||||
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
|
||||
let OverloadedName = "vfncvt_x" in
|
||||
defm :
|
||||
@ -2410,7 +2410,7 @@ let ManualCodegen = [{
|
||||
}
|
||||
}
|
||||
|
||||
// 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions
|
||||
// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
|
||||
let OverloadedName = "vfcvt_x" in
|
||||
defm :
|
||||
RVVConvBuiltinSet<"vfcvt_x_f_v", "xfd", [["Iv", "Ivv"]]>;
|
||||
@ -2424,7 +2424,7 @@ let ManualCodegen = [{
|
||||
RVVConvBuiltinSet<"vfcvt_f_xu_v", "sil", [["Fv", "FvUv"]]>;
|
||||
}
|
||||
|
||||
// 14.18. Widening Floating-Point/Integer Type-Convert Instructions
|
||||
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
|
||||
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
|
||||
let OverloadedName = "vfwcvt_x" in
|
||||
defm :
|
||||
@ -2433,7 +2433,7 @@ let ManualCodegen = [{
|
||||
defm :
|
||||
RVVConvBuiltinSet<"vfwcvt_xu_f_v", "xf", [["Uw", "Uwv"]]>;
|
||||
}
|
||||
// 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
|
||||
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
|
||||
let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
|
||||
let OverloadedName = "vfncvt_x" in
|
||||
defm :
|
||||
@ -2456,8 +2456,8 @@ let ManualCodegen = [{
|
||||
}
|
||||
}
|
||||
|
||||
// 15. Vector Reduction Operations
|
||||
// 15.1. Vector Single-Width Integer Reduction Instructions
|
||||
// 14. Vector Reduction Operations
|
||||
// 14.1. Vector Single-Width Integer Reduction Instructions
|
||||
let UnMaskedPolicyScheme = HasPassthruOperand,
|
||||
MaskedPolicyScheme = HasPassthruOperand,
|
||||
HasMaskPolicy = false in {
|
||||
@ -2470,7 +2470,7 @@ defm vredand : RVVIntReductionBuiltinSet;
|
||||
defm vredor : RVVIntReductionBuiltinSet;
|
||||
defm vredxor : RVVIntReductionBuiltinSet;
|
||||
|
||||
// 15.2. Vector Widening Integer Reduction Instructions
|
||||
// 14.2. Vector Widening Integer Reduction Instructions
|
||||
// Vector Widening Integer Reduction Operations
|
||||
let HasMaskedOffOperand = true in {
|
||||
defm vwredsum : RVVOutOp0BuiltinSet<"vwredsum", "csi",
|
||||
@ -2479,7 +2479,7 @@ let HasMaskedOffOperand = true in {
|
||||
[["vs", "UvUSw", "USwUvUSw"]]>;
|
||||
}
|
||||
|
||||
// 15.3. Vector Single-Width Floating-Point Reduction Instructions
|
||||
// 14.3. Vector Single-Width Floating-Point Reduction Instructions
|
||||
defm vfredmax : RVVFloatingReductionBuiltin;
|
||||
defm vfredmin : RVVFloatingReductionBuiltin;
|
||||
let ManualCodegen = [{
|
||||
@ -2525,26 +2525,26 @@ let ManualCodegen = [{
|
||||
}
|
||||
}] in {
|
||||
let HasFRMRoundModeOp = 1 in {
|
||||
// 15.3. Vector Single-Width Floating-Point Reduction Instructions
|
||||
// 14.3. Vector Single-Width Floating-Point Reduction Instructions
|
||||
defm vfredusum : RVVFloatingReductionBuiltinRoundingMode;
|
||||
defm vfredosum : RVVFloatingReductionBuiltinRoundingMode;
|
||||
|
||||
// 15.4. Vector Widening Floating-Point Reduction Instructions
|
||||
// 14.4. Vector Widening Floating-Point Reduction Instructions
|
||||
defm vfwredusum : RVVFloatingWidenReductionBuiltinRoundingMode;
|
||||
defm vfwredosum : RVVFloatingWidenReductionBuiltinRoundingMode;
|
||||
}
|
||||
// 15.3. Vector Single-Width Floating-Point Reduction Instructions
|
||||
// 14.3. Vector Single-Width Floating-Point Reduction Instructions
|
||||
defm vfredusum : RVVFloatingReductionBuiltin;
|
||||
defm vfredosum : RVVFloatingReductionBuiltin;
|
||||
|
||||
// 15.4. Vector Widening Floating-Point Reduction Instructions
|
||||
// 14.4. Vector Widening Floating-Point Reduction Instructions
|
||||
defm vfwredusum : RVVFloatingWidenReductionBuiltin;
|
||||
defm vfwredosum : RVVFloatingWidenReductionBuiltin;
|
||||
}
|
||||
}
|
||||
|
||||
// 16. Vector Mask Instructions
|
||||
// 16.1. Vector Mask-Register Logical Instructions
|
||||
// 15. Vector Mask Instructions
|
||||
// 15.1. Vector Mask-Register Logical Instructions
|
||||
def vmand : RVVMaskBinBuiltin;
|
||||
def vmnand : RVVMaskBinBuiltin;
|
||||
def vmandn : RVVMaskBinBuiltin;
|
||||
@ -2560,36 +2560,36 @@ defm vmmv_m : RVVPseudoMaskBuiltin<"vmand", "c">;
|
||||
defm vmnot_m : RVVPseudoMaskBuiltin<"vmnand", "c">;
|
||||
|
||||
let MaskedPolicyScheme = NonePolicy in {
|
||||
// 16.2. Vector count population in mask vcpop.m
|
||||
// 15.2. Vector count population in mask vcpop.m
|
||||
def vcpop : RVVMaskOp0Builtin<"um">;
|
||||
|
||||
// 16.3. vfirst find-first-set mask bit
|
||||
// 15.3. vfirst find-first-set mask bit
|
||||
def vfirst : RVVMaskOp0Builtin<"lm">;
|
||||
}
|
||||
|
||||
let MaskedPolicyScheme = HasPassthruOperand,
|
||||
HasTailPolicy = false in {
|
||||
// 16.4. vmsbf.m set-before-first mask bit
|
||||
// 15.4. vmsbf.m set-before-first mask bit
|
||||
def vmsbf : RVVMaskUnaryBuiltin;
|
||||
|
||||
// 16.5. vmsif.m set-including-first mask bit
|
||||
// 15.5. vmsif.m set-including-first mask bit
|
||||
def vmsif : RVVMaskUnaryBuiltin;
|
||||
|
||||
// 16.6. vmsof.m set-only-first mask bit
|
||||
// 15.6. vmsof.m set-only-first mask bit
|
||||
def vmsof : RVVMaskUnaryBuiltin;
|
||||
}
|
||||
|
||||
let UnMaskedPolicyScheme = HasPassthruOperand, SupportOverloading = false in {
|
||||
// 16.8. Vector Iota Instruction
|
||||
// 15.8. Vector Iota Instruction
|
||||
defm viota : RVVOutBuiltinSet<"viota", "csil", [["m", "Uv", "Uvm"]]>;
|
||||
|
||||
// 16.9. Vector Element Index Instruction
|
||||
// 15.9. Vector Element Index Instruction
|
||||
defm vid : RVVOutBuiltinSet<"vid", "csil", [["v", "v", "v"],
|
||||
["v", "Uv", "Uv"]]>;
|
||||
}
|
||||
|
||||
// 17. Vector Permutation Instructions
|
||||
// 17.1. Integer Scalar Move Instructions
|
||||
// 16. Vector Permutation Instructions
|
||||
// 16.1. Integer Scalar Move Instructions
|
||||
let HasMasked = false, MaskedPolicyScheme = NonePolicy in {
|
||||
let HasVL = false, OverloadedName = "vmv_x" in
|
||||
defm vmv_x : RVVOp0BuiltinSet<"vmv_x_s", "csil",
|
||||
@ -2603,7 +2603,7 @@ let HasMasked = false, MaskedPolicyScheme = NonePolicy in {
|
||||
["x", "Uv", "UvUe"]]>;
|
||||
}
|
||||
|
||||
// 17.2. Floating-Point Scalar Move Instructions
|
||||
// 16.2. Floating-Point Scalar Move Instructions
|
||||
let HasMasked = false, MaskedPolicyScheme = NonePolicy in {
|
||||
let HasVL = false, OverloadedName = "vfmv_f" in
|
||||
defm vfmv_f : RVVOp0BuiltinSet<"vfmv_f_s", "xfd",
|
||||
@ -2616,22 +2616,22 @@ let HasMasked = false, MaskedPolicyScheme = NonePolicy in {
|
||||
["x", "Uv", "UvUe"]]>;
|
||||
}
|
||||
|
||||
// 17.3. Vector Slide Instructions
|
||||
// 17.3.1. Vector Slideup Instructions
|
||||
// 16.3. Vector Slide Instructions
|
||||
// 16.3.1. Vector Slideup Instructions
|
||||
defm vslideup : RVVSlideUpBuiltinSet;
|
||||
// 17.3.2. Vector Slidedown Instructions
|
||||
// 16.3.2. Vector Slidedown Instructions
|
||||
defm vslidedown : RVVSlideDownBuiltinSet;
|
||||
|
||||
// 17.3.3. Vector Slide1up Instructions
|
||||
// 16.3.3. Vector Slide1up Instructions
|
||||
let UnMaskedPolicyScheme = HasPassthruOperand in {
|
||||
defm vslide1up : RVVSlideOneBuiltinSet;
|
||||
defm vfslide1up : RVVFloatingBinVFBuiltinSet;
|
||||
|
||||
// 17.3.4. Vector Slide1down Instruction
|
||||
// 16.3.4. Vector Slide1down Instruction
|
||||
defm vslide1down : RVVSlideOneBuiltinSet;
|
||||
defm vfslide1down : RVVFloatingBinVFBuiltinSet;
|
||||
|
||||
// 17.4. Vector Register Gather Instructions
|
||||
// 16.4. Vector Register Gather Instructions
|
||||
// signed and floating type
|
||||
defm vrgather : RVVOutBuiltinSet<"vrgather_vv", "csilxfd",
|
||||
[["vv", "v", "vvUv"]]>;
|
||||
@ -2648,7 +2648,7 @@ defm vrgatherei16 : RVVOutBuiltinSet<"vrgatherei16_vv", "csil",
|
||||
[["vv", "Uv", "UvUv(Log2EEW:4)Uv"]]>;
|
||||
}
|
||||
|
||||
// 17.5. Vector Compress Instruction
|
||||
// 16.5. Vector Compress Instruction
|
||||
let HasMasked = false,
|
||||
UnMaskedPolicyScheme = HasPassthruOperand,
|
||||
MaskedPolicyScheme = NonePolicy,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user