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[PhaseOrdering] add test for vectorizer cooperation; NFC
This would potentially change with the proposal in D81416.
This commit is contained in:
Sanjay Patel
parent
264f0dbef8
commit
df794431e0
220
llvm/test/Transforms/PhaseOrdering/interleave-vectorization.ll
Normal file
220
llvm/test/Transforms/PhaseOrdering/interleave-vectorization.ll
Normal file
@ -0,0 +1,220 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; REQUIRES: powerpc-registered-target
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; RUN: opt < %s -O2 -S -mcpu=pwr9 | FileCheck %s
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; RUN: opt < %s -passes='default<O2>' -S -mcpu=pwr9 | FileCheck %s
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;void fun(Vector<double> &MatrixB,
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; const Vector<double> &MatrixA,
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; const unsigned int * const start,
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; const unsigned int * const end,
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; const double * val) const
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;{
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; const unsigned int N=MatrixB.size();
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; MatrixB = MatrixA;
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; for (unsigned int row=0; row<N; ++row)
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; {
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; double sum = 0;
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; for (const unsigned int * col=start; col!=end; ++col, ++val)
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; sum += *val * MatrixB(*col);
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; MatrixB(row) -= sum;
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; }
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;}
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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%0 = type { %1, %8 }
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%1 = type { %2, i8, double, %4, %7* }
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%2 = type <{ i32 (...)**, %3, double*, i32 }>
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%3 = type { %7*, i8* }
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%4 = type { %5 }
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%5 = type { %6 }
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%6 = type { i32**, i32**, i32** }
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%7 = type <{ %8, i32, i32, i32, [4 x i8], i64, i32, [4 x i8], i64*, i32*, i8, i8, [6 x i8] }>
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%8 = type { i32 (...)**, i32, %9, %16* }
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%9 = type { %10 }
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%10 = type { %11 }
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%11 = type { %12, %14 }
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%12 = type { %13 }
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%13 = type { i8 }
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%14 = type { %15, i64 }
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%15 = type { i32, %15*, %15*, %15* }
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%16 = type { i32 (...)**, i8* }
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%17 = type { %8, i32, i32, double* }
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$test = comdat any
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define void @test(%0* %arg, %17* dereferenceable(88) %arg1) comdat align 2 {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: [[T14:%.*]] = getelementptr [[TMP0:%.*]], %0* [[ARG:%.*]], i64 0, i32 0, i32 3, i32 0, i32 0, i32 0
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; CHECK-NEXT: [[T15:%.*]] = load i32**, i32*** [[T14]], align 8
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; CHECK-NEXT: [[T18:%.*]] = getelementptr inbounds [[TMP17:%.*]], %17* [[ARG1:%.*]], i64 0, i32 3
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; CHECK-NEXT: [[T19:%.*]] = load double*, double** [[T18]], align 8
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; CHECK-NEXT: [[T28:%.*]] = getelementptr inbounds i32*, i32** [[T15]], i64 undef
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; CHECK-NEXT: [[T35:%.*]] = getelementptr inbounds double, double* [[T19]], i64 undef
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; CHECK-NEXT: br label [[BB22:%.*]]
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; CHECK: bb22:
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; CHECK-NEXT: [[T29:%.*]] = load i32*, i32** [[T28]], align 8
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; CHECK-NEXT: [[UGLYGEP9:%.*]] = getelementptr i32, i32* [[T29]], i64 -2
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; CHECK-NEXT: [[UGLYGEP2:%.*]] = ptrtoint i32* [[UGLYGEP9]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[UGLYGEP2]], 2
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; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp eq i64 [[TMP1]], 0
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[BB40_PREHEADER:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: bb40.preheader:
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; CHECK-NEXT: [[T41_PH:%.*]] = phi i32* [ inttoptr (i64 4 to i32*), [[BB22]] ], [ [[IND_END:%.*]], [[MIDDLE_BLOCK:%.*]] ]
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; CHECK-NEXT: [[T42_PH:%.*]] = phi double* [ inttoptr (i64 8 to double*), [[BB22]] ], [ [[IND_END4:%.*]], [[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: [[T43_PH:%.*]] = phi double [ 0.000000e+00, [[BB22]] ], [ [[BIN_RDX:%.*]], [[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: br label [[BB40:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP2]], 9223372036854775806
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; CHECK-NEXT: [[IND_END]] = getelementptr i32, i32* inttoptr (i64 4 to i32*), i64 [[N_VEC]]
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; CHECK-NEXT: [[IND_END4]] = getelementptr double, double* inttoptr (i64 8 to double*), i64 [[N_VEC]]
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; CHECK-NEXT: [[TMP3:%.*]] = add nsw i64 [[N_VEC]], -2
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; CHECK-NEXT: [[TMP4:%.*]] = lshr exact i64 [[TMP3]], 1
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; CHECK-NEXT: [[TMP5:%.*]] = add nuw i64 [[TMP4]], 1
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; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[TMP5]], 1
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP3]], 0
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; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK_UNR_LCSSA:%.*]], label [[VECTOR_PH_NEW:%.*]]
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; CHECK: vector.ph.new:
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; CHECK-NEXT: [[UNROLL_ITER:%.*]] = and i64 [[TMP5]], -2
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH_NEW]] ], [ [[INDEX_NEXT_1:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI:%.*]] = phi double [ 0.000000e+00, [[VECTOR_PH_NEW]] ], [ [[TMP37:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI8:%.*]] = phi double [ 0.000000e+00, [[VECTOR_PH_NEW]] ], [ [[TMP38:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ [[UNROLL_ITER]], [[VECTOR_PH_NEW]] ], [ [[NITER_NSUB_1:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i32, i32* inttoptr (i64 4 to i32*), i64 [[INDEX]]
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; CHECK-NEXT: [[TMP7:%.*]] = or i64 [[INDEX]], 1
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; CHECK-NEXT: [[NEXT_GEP5:%.*]] = getelementptr i32, i32* inttoptr (i64 4 to i32*), i64 [[TMP7]]
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; CHECK-NEXT: [[NEXT_GEP6:%.*]] = getelementptr double, double* inttoptr (i64 8 to double*), i64 [[INDEX]]
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; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[INDEX]], 1
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; CHECK-NEXT: [[NEXT_GEP7:%.*]] = getelementptr double, double* inttoptr (i64 8 to double*), i64 [[TMP8]]
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; CHECK-NEXT: [[TMP9:%.*]] = load double, double* [[NEXT_GEP6]], align 8
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; CHECK-NEXT: [[TMP10:%.*]] = load double, double* [[NEXT_GEP7]], align 8
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; CHECK-NEXT: [[TMP11:%.*]] = load i32, i32* [[NEXT_GEP]], align 4
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; CHECK-NEXT: [[TMP12:%.*]] = load i32, i32* [[NEXT_GEP5]], align 4
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; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP11]] to i64
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; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[TMP12]] to i64
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; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds double, double* [[T19]], i64 [[TMP13]]
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; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds double, double* [[T19]], i64 [[TMP14]]
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; CHECK-NEXT: [[TMP17]] = load double, double* [[TMP15]], align 8
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; CHECK-NEXT: [[TMP18:%.*]] = load double, double* [[TMP16]], align 8
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; CHECK-NEXT: [[TMP19:%.*]] = fmul fast double [[TMP17]], [[TMP9]]
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; CHECK-NEXT: [[TMP20:%.*]] = fmul fast double [[TMP18]], [[TMP10]]
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; CHECK-NEXT: [[TMP21:%.*]] = fadd fast double [[TMP19]], [[VEC_PHI]]
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; CHECK-NEXT: [[TMP22:%.*]] = fadd fast double [[TMP20]], [[VEC_PHI8]]
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; CHECK-NEXT: [[INDEX_NEXT:%.*]] = or i64 [[INDEX]], 2
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; CHECK-NEXT: [[NEXT_GEP_1:%.*]] = getelementptr i32, i32* inttoptr (i64 4 to i32*), i64 [[INDEX_NEXT]]
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; CHECK-NEXT: [[TMP23:%.*]] = or i64 [[INDEX]], 3
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; CHECK-NEXT: [[NEXT_GEP5_1:%.*]] = getelementptr i32, i32* inttoptr (i64 4 to i32*), i64 [[TMP23]]
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; CHECK-NEXT: [[NEXT_GEP6_1:%.*]] = getelementptr double, double* inttoptr (i64 8 to double*), i64 [[INDEX_NEXT]]
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; CHECK-NEXT: [[TMP24:%.*]] = or i64 [[INDEX]], 3
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; CHECK-NEXT: [[NEXT_GEP7_1:%.*]] = getelementptr double, double* inttoptr (i64 8 to double*), i64 [[TMP24]]
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; CHECK-NEXT: [[TMP25:%.*]] = load double, double* [[NEXT_GEP6_1]], align 8
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; CHECK-NEXT: [[TMP26:%.*]] = load double, double* [[NEXT_GEP7_1]], align 8
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; CHECK-NEXT: [[TMP27:%.*]] = load i32, i32* [[NEXT_GEP_1]], align 4
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; CHECK-NEXT: [[TMP28:%.*]] = load i32, i32* [[NEXT_GEP5_1]], align 4
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; CHECK-NEXT: [[TMP29:%.*]] = zext i32 [[TMP27]] to i64
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; CHECK-NEXT: [[TMP30:%.*]] = zext i32 [[TMP28]] to i64
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; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds double, double* [[T19]], i64 [[TMP29]]
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; CHECK-NEXT: [[TMP32:%.*]] = getelementptr inbounds double, double* [[T19]], i64 [[TMP30]]
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; CHECK-NEXT: [[TMP33:%.*]] = load double, double* [[TMP31]], align 8
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; CHECK-NEXT: [[TMP34:%.*]] = load double, double* [[TMP32]], align 8
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; CHECK-NEXT: [[TMP35:%.*]] = fmul fast double [[TMP33]], [[TMP25]]
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; CHECK-NEXT: [[TMP36:%.*]] = fmul fast double [[TMP34]], [[TMP26]]
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; CHECK-NEXT: [[TMP37]] = fadd fast double [[TMP35]], [[TMP21]]
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; CHECK-NEXT: [[TMP38]] = fadd fast double [[TMP36]], [[TMP22]]
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; CHECK-NEXT: [[INDEX_NEXT_1]] = add i64 [[INDEX]], 4
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; CHECK-NEXT: [[NITER_NSUB_1]] = add i64 [[NITER]], -2
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; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NSUB_1]], 0
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; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[MIDDLE_BLOCK_UNR_LCSSA]], label [[VECTOR_BODY]], !llvm.loop !0
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; CHECK: middle.block.unr-lcssa:
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; CHECK-NEXT: [[DOTLCSSA10_PH:%.*]] = phi double [ undef, [[VECTOR_PH]] ], [ [[TMP37]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[DOTLCSSA_PH:%.*]] = phi double [ undef, [[VECTOR_PH]] ], [ [[TMP38]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[INDEX_UNR:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT_1]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI_UNR:%.*]] = phi double [ 0.000000e+00, [[VECTOR_PH]] ], [ [[TMP37]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI8_UNR:%.*]] = phi double [ 0.000000e+00, [[VECTOR_PH]] ], [ [[TMP38]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp eq i64 [[XTRAITER]], 0
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; CHECK-NEXT: br i1 [[LCMP_MOD]], label [[MIDDLE_BLOCK]], label [[MIDDLE_BLOCK_EPILOG_LCSSA:%.*]]
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; CHECK: middle.block.epilog-lcssa:
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; CHECK-NEXT: [[TMP39:%.*]] = or i64 [[INDEX_UNR]], 1
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; CHECK-NEXT: [[NEXT_GEP5_EPIL:%.*]] = getelementptr i32, i32* inttoptr (i64 4 to i32*), i64 [[TMP39]]
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; CHECK-NEXT: [[TMP40:%.*]] = load i32, i32* [[NEXT_GEP5_EPIL]], align 4
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; CHECK-NEXT: [[TMP41:%.*]] = zext i32 [[TMP40]] to i64
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; CHECK-NEXT: [[TMP42:%.*]] = getelementptr inbounds double, double* [[T19]], i64 [[TMP41]]
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; CHECK-NEXT: [[TMP43:%.*]] = load double, double* [[TMP42]], align 8
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; CHECK-NEXT: [[TMP44:%.*]] = or i64 [[INDEX_UNR]], 1
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; CHECK-NEXT: [[NEXT_GEP7_EPIL:%.*]] = getelementptr double, double* inttoptr (i64 8 to double*), i64 [[TMP44]]
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; CHECK-NEXT: [[TMP45:%.*]] = load double, double* [[NEXT_GEP7_EPIL]], align 8
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; CHECK-NEXT: [[TMP46:%.*]] = fmul fast double [[TMP43]], [[TMP45]]
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; CHECK-NEXT: [[TMP47:%.*]] = fadd fast double [[TMP46]], [[VEC_PHI8_UNR]]
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; CHECK-NEXT: [[NEXT_GEP_EPIL:%.*]] = getelementptr i32, i32* inttoptr (i64 4 to i32*), i64 [[INDEX_UNR]]
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; CHECK-NEXT: [[TMP48:%.*]] = load i32, i32* [[NEXT_GEP_EPIL]], align 4
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; CHECK-NEXT: [[TMP49:%.*]] = zext i32 [[TMP48]] to i64
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; CHECK-NEXT: [[TMP50:%.*]] = getelementptr inbounds double, double* [[T19]], i64 [[TMP49]]
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; CHECK-NEXT: [[TMP51:%.*]] = load double, double* [[TMP50]], align 8
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; CHECK-NEXT: [[NEXT_GEP6_EPIL:%.*]] = getelementptr double, double* inttoptr (i64 8 to double*), i64 [[INDEX_UNR]]
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; CHECK-NEXT: [[TMP52:%.*]] = load double, double* [[NEXT_GEP6_EPIL]], align 8
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; CHECK-NEXT: [[TMP53:%.*]] = fmul fast double [[TMP51]], [[TMP52]]
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; CHECK-NEXT: [[TMP54:%.*]] = fadd fast double [[TMP53]], [[VEC_PHI_UNR]]
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; CHECK-NEXT: br label [[MIDDLE_BLOCK]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[DOTLCSSA10:%.*]] = phi double [ [[DOTLCSSA10_PH]], [[MIDDLE_BLOCK_UNR_LCSSA]] ], [ [[TMP54]], [[MIDDLE_BLOCK_EPILOG_LCSSA]] ]
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; CHECK-NEXT: [[DOTLCSSA:%.*]] = phi double [ [[DOTLCSSA_PH]], [[MIDDLE_BLOCK_UNR_LCSSA]] ], [ [[TMP47]], [[MIDDLE_BLOCK_EPILOG_LCSSA]] ]
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; CHECK-NEXT: [[BIN_RDX]] = fadd fast double [[DOTLCSSA]], [[DOTLCSSA10]]
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label [[BB33:%.*]], label [[BB40_PREHEADER]]
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; CHECK: bb33:
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; CHECK-NEXT: [[T50_LCSSA:%.*]] = phi double [ [[BIN_RDX]], [[MIDDLE_BLOCK]] ], [ [[T50:%.*]], [[BB40]] ]
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; CHECK-NEXT: [[T37:%.*]] = fneg fast double [[T50_LCSSA]]
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; CHECK-NEXT: store double [[T37]], double* [[T35]], align 8
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; CHECK-NEXT: br label [[BB22]]
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; CHECK: bb40:
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; CHECK-NEXT: [[T41:%.*]] = phi i32* [ [[T51:%.*]], [[BB40]] ], [ [[T41_PH]], [[BB40_PREHEADER]] ]
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; CHECK-NEXT: [[T42:%.*]] = phi double* [ [[T52:%.*]], [[BB40]] ], [ [[T42_PH]], [[BB40_PREHEADER]] ]
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; CHECK-NEXT: [[T43:%.*]] = phi double [ [[T50]], [[BB40]] ], [ [[T43_PH]], [[BB40_PREHEADER]] ]
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; CHECK-NEXT: [[T44:%.*]] = load double, double* [[T42]], align 8
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; CHECK-NEXT: [[T45:%.*]] = load i32, i32* [[T41]], align 4
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; CHECK-NEXT: [[T46:%.*]] = zext i32 [[T45]] to i64
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; CHECK-NEXT: [[T47:%.*]] = getelementptr inbounds double, double* [[T19]], i64 [[T46]]
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; CHECK-NEXT: [[T48:%.*]] = load double, double* [[T47]], align 8
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; CHECK-NEXT: [[T49:%.*]] = fmul fast double [[T48]], [[T44]]
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; CHECK-NEXT: [[T50]] = fadd fast double [[T49]], [[T43]]
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; CHECK-NEXT: [[T51]] = getelementptr inbounds i32, i32* [[T41]], i64 1
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; CHECK-NEXT: [[T52]] = getelementptr inbounds double, double* [[T42]], i64 1
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; CHECK-NEXT: [[T53:%.*]] = icmp eq i32* [[T51]], [[T29]]
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; CHECK-NEXT: br i1 [[T53]], label [[BB33]], label [[BB40]], !llvm.loop !2
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;
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%t14 = getelementptr %0, %0* %arg, i64 0, i32 0, i32 3, i32 0, i32 0, i32 0
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%t15 = load i32**, i32*** %t14, align 8
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%t18 = getelementptr inbounds %17, %17* %arg1, i64 0, i32 3
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%t19 = load double*, double** %t18, align 8
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br label %bb22
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bb22:
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%t26 = add i64 0, 1
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%t27 = getelementptr inbounds i32, i32* null, i64 %t26
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%t28 = getelementptr inbounds i32*, i32** %t15, i64 undef
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%t29 = load i32*, i32** %t28, align 8
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%t32 = getelementptr inbounds double, double* null, i64 %t26
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br label %bb40
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bb33:
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%t35 = getelementptr inbounds double, double* %t19, i64 undef
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%t37 = fsub fast double 0.000000e+00, %t50
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store double %t37, double* %t35, align 8
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br label %bb22
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bb40:
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%t41 = phi i32* [ %t51, %bb40 ], [ %t27, %bb22 ]
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%t42 = phi double* [ %t52, %bb40 ], [ %t32, %bb22 ]
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%t43 = phi double [ %t50, %bb40 ], [ 0.000000e+00, %bb22 ]
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%t44 = load double, double* %t42, align 8
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%t45 = load i32, i32* %t41, align 4
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%t46 = zext i32 %t45 to i64
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%t47 = getelementptr inbounds double, double* %t19, i64 %t46
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%t48 = load double, double* %t47, align 8
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%t49 = fmul fast double %t48, %t44
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%t50 = fadd fast double %t49, %t43
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%t51 = getelementptr inbounds i32, i32* %t41, i64 1
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%t52 = getelementptr inbounds double, double* %t42, i64 1
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%t53 = icmp eq i32* %t51, %t29
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br i1 %t53, label %bb33, label %bb40
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}
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