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[Hexagon] Properly handle instruction selection of vsplat intrinsics

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llvm-svn: 269312
This commit is contained in:
Krzysztof Parzyszek 2016-05-12 17:21:40 +00:00
parent 7a947b6c6d
commit e60e5fee0a
2 changed files with 13 additions and 2 deletions
llvm
lib/Target/Hexagon
HexagonISelDAGToDAG.cpp
test/CodeGen/Hexagon
vsplat-isel.ll

5
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp

@ -1044,11 +1044,12 @@ SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
return SelectCode(N); return SelectCode(N);
} }
SDValue const &V = N->getOperand(1); SDValue V = N->getOperand(1);
SDValue U; SDValue U;
if (isValueExtension(V, Bits, U)) { if (isValueExtension(V, Bits, U)) {
SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
N->getOperand(0), U); N->getOperand(0), U);
ReplaceUses(N, R.getNode());
return SelectCode(R.getNode()); return SelectCode(R.getNode());
} }
return SelectCode(N); return SelectCode(N);

10
llvm/test/CodeGen/Hexagon/vsplat-isel.ll Normal file

@ -0,0 +1,10 @@
; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
; CHECK: vsplatb
declare i32 @llvm.hexagon.S2.vsplatrb(i32) #0
define i32 @foo(i8 %x) {
%p0 = zext i8 %x to i32
%p1 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %p0)
ret i32 %p1
}