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Define selection for v4f16, v8f16 scalar_to_vector

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Summary:
This fixes failure when trying to select
    insertelement <4 x half> undef, half %a, i64 0
which gets transformed to a scalar_to_vector node.

The accompanying v4 and v8 tests fail instruction selection without this
patch.

Reviewers: ab, jmolloy

Subscribers: srhines, llvm-commits

Differential Revision: http://reviews.llvm.org/D15322

llvm-svn: 255072
This commit is contained in:
Pirama Arumuga Nainar 2015-12-08 23:07:06 +00:00
parent 5411d0510c
commit e6ccd7b66a
3 changed files with 23 additions and 0 deletions
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5
llvm/lib/Target/AArch64/AArch64InstrInfo.td
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@ -3843,6 +3843,11 @@ def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
(v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
(i64 FPR64:$Rn), dsub))>;
def : Pat<(v4f16 (scalar_to_vector (f16 FPR16:$Rn))),
(INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
def : Pat<(v8f16 (scalar_to_vector (f16 FPR16:$Rn))),
(INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),

9
llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll
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@ -218,4 +218,13 @@ define <4 x half> @uitofp_i64(<4 x i64> %a) #0 {
ret <4 x half> %1
}
define void @test_insert_at_zero(half %a, <4 x half>* %b) #0 {
; CHECK-LABEL: test_insert_at_zero:
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
%1 = insertelement <4 x half> undef, half %a, i64 0
store <4 x half> %1, <4 x half>* %b, align 4
ret void
}
attributes #0 = { nounwind }

9
llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
View File

@ -358,4 +358,13 @@ define <8 x half> @uitofp_i64(<8 x i64> %a) #0 {
ret <8 x half> %1
}
define void @test_insert_at_zero(half %a, <8 x half>* %b) #0 {
; CHECK-LABEL: test_insert_at_zero:
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
%1 = insertelement <8 x half> undef, half %a, i64 0
store <8 x half> %1, <8 x half>* %b, align 4
ret void
}
attributes #0 = { nounwind }