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[AMDGPU] Select buffer_atomic_cmpswap* in tblgen
This change replaces the manual selection of buffer_atomic_cmpswap* instructions in SelectionDAG and GlobalISel with a tblgen based selection in BUFInstructions.td. This allows us to select the return and no-return variants in tblgen. Differential Revision: https://reviews.llvm.org/D121770
This commit is contained in:
Abinav Puthan Purayil
parent
557a0e7b96
commit
f59cb41ba1
@ -679,9 +679,6 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) {
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case ISD::FMA:
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SelectFMAD_FMA(N);
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return;
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case AMDGPUISD::ATOMIC_CMP_SWAP:
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SelectATOMIC_CMP_SWAP(N);
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return;
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case AMDGPUISD::CVT_PKRTZ_F16_F32:
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case AMDGPUISD::CVT_PKNORM_I16_F32:
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case AMDGPUISD::CVT_PKNORM_U16_F32:
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@ -2278,70 +2275,6 @@ void AMDGPUDAGToDAGISel::SelectFMAD_FMA(SDNode *N) {
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}
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}
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// This is here because there isn't a way to use the generated sub0_sub1 as the
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// subreg index to EXTRACT_SUBREG in tablegen.
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void AMDGPUDAGToDAGISel::SelectATOMIC_CMP_SWAP(SDNode *N) {
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MemSDNode *Mem = cast<MemSDNode>(N);
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unsigned AS = Mem->getAddressSpace();
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if (AS == AMDGPUAS::FLAT_ADDRESS) {
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SelectCode(N);
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return;
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}
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MVT VT = N->getSimpleValueType(0);
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bool Is32 = (VT == MVT::i32);
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SDLoc SL(N);
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MachineSDNode *CmpSwap = nullptr;
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if (Subtarget->hasAddr64()) {
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SDValue SRsrc, VAddr, SOffset, Offset;
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if (SelectMUBUFAddr64(Mem->getBasePtr(), SRsrc, VAddr, SOffset, Offset)) {
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unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN :
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AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN;
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SDValue CmpVal = Mem->getOperand(2);
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SDValue CPol = CurDAG->getTargetConstant(AMDGPU::CPol::GLC, SL, MVT::i32);
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// XXX - Do we care about glue operands?
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SDValue Ops[] = {CmpVal, VAddr, SRsrc, SOffset, Offset, CPol,
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Mem->getChain()};
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CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops);
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}
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}
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if (!CmpSwap) {
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SDValue SRsrc, SOffset, Offset;
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if (SelectMUBUFOffset(Mem->getBasePtr(), SRsrc, SOffset, Offset)) {
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unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN :
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AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN;
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SDValue CmpVal = Mem->getOperand(2);
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SDValue CPol = CurDAG->getTargetConstant(AMDGPU::CPol::GLC, SL, MVT::i32);
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SDValue Ops[] = {CmpVal, SRsrc, SOffset, Offset, CPol, Mem->getChain()};
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CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops);
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}
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}
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if (!CmpSwap) {
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SelectCode(N);
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return;
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}
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MachineMemOperand *MMO = Mem->getMemOperand();
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CurDAG->setNodeMemRefs(CmpSwap, {MMO});
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unsigned SubReg = Is32 ? AMDGPU::sub0 : AMDGPU::sub0_sub1;
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SDValue Extract
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= CurDAG->getTargetExtractSubreg(SubReg, SL, VT, SDValue(CmpSwap, 0));
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ReplaceUses(SDValue(N, 0), Extract);
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ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 1));
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CurDAG->RemoveDeadNode(N);
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}
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void AMDGPUDAGToDAGISel::SelectDSAppendConsume(SDNode *N, unsigned IntrID) {
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// The address is assumed to be uniform, so if it ends up in a VGPR, it will
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// be copied to an SGPR with readfirstlane.
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@ -249,7 +249,6 @@ private:
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bool isCBranchSCC(const SDNode *N) const;
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void SelectBRCOND(SDNode *N);
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void SelectFMAD_FMA(SDNode *N);
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void SelectATOMIC_CMP_SWAP(SDNode *N);
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void SelectDSAppendConsume(SDNode *N, unsigned IntrID);
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void SelectDS_GWS(SDNode *N, unsigned IntrID);
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void SelectInterpP1F16(SDNode *N);
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@ -2385,65 +2385,6 @@ bool AMDGPUInstructionSelector::selectG_LOAD_STORE_ATOMICRMW(
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return selectImpl(I, *CoverageInfo);
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}
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// TODO: No rtn optimization.
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bool AMDGPUInstructionSelector::selectG_AMDGPU_ATOMIC_CMPXCHG(
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MachineInstr &MI) const {
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Register PtrReg = MI.getOperand(1).getReg();
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const LLT PtrTy = MRI->getType(PtrReg);
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if (PtrTy.getAddressSpace() == AMDGPUAS::FLAT_ADDRESS ||
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STI.useFlatForGlobal())
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return selectImpl(MI, *CoverageInfo);
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Register DstReg = MI.getOperand(0).getReg();
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const LLT Ty = MRI->getType(DstReg);
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const bool Is64 = Ty.getSizeInBits() == 64;
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const unsigned SubReg = Is64 ? AMDGPU::sub0_sub1 : AMDGPU::sub0;
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Register TmpReg = MRI->createVirtualRegister(
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Is64 ? &AMDGPU::VReg_128RegClass : &AMDGPU::VReg_64RegClass);
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const DebugLoc &DL = MI.getDebugLoc();
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MachineBasicBlock *BB = MI.getParent();
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Register VAddr, RSrcReg, SOffset;
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int64_t Offset = 0;
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unsigned Opcode;
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if (selectMUBUFOffsetImpl(MI.getOperand(1), RSrcReg, SOffset, Offset)) {
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Opcode = Is64 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN :
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AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN;
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} else if (selectMUBUFAddr64Impl(MI.getOperand(1), VAddr,
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RSrcReg, SOffset, Offset)) {
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Opcode = Is64 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN :
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AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN;
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} else
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return selectImpl(MI, *CoverageInfo);
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auto MIB = BuildMI(*BB, &MI, DL, TII.get(Opcode), TmpReg)
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.addReg(MI.getOperand(2).getReg());
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if (VAddr)
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MIB.addReg(VAddr);
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MIB.addReg(RSrcReg);
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if (SOffset)
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MIB.addReg(SOffset);
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else
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MIB.addImm(0);
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MIB.addImm(Offset);
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MIB.addImm(AMDGPU::CPol::GLC);
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MIB.cloneMemRefs(MI);
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BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), DstReg)
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.addReg(TmpReg, RegState::Kill, SubReg);
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MI.eraseFromParent();
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MRI->setRegClass(
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DstReg, Is64 ? &AMDGPU::VReg_64RegClass : &AMDGPU::VGPR_32RegClass);
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return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
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}
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static bool isVCmpResult(Register Reg, MachineRegisterInfo &MRI) {
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if (Reg.isPhysical())
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return false;
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@ -3227,8 +3168,6 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
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case AMDGPU::G_AMDGPU_ATOMIC_FMIN:
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case AMDGPU::G_AMDGPU_ATOMIC_FMAX:
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return selectG_LOAD_STORE_ATOMICRMW(I);
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case AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG:
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return selectG_AMDGPU_ATOMIC_CMPXCHG(I);
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case TargetOpcode::G_SELECT:
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return selectG_SELECT(I);
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case TargetOpcode::G_TRUNC:
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@ -133,7 +133,6 @@ private:
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void initM0(MachineInstr &I) const;
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bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
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bool selectG_AMDGPU_ATOMIC_CMPXCHG(MachineInstr &I) const;
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bool selectG_SELECT(MachineInstr &I) const;
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bool selectG_BRCOND(MachineInstr &I) const;
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bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
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@ -1399,6 +1399,37 @@ multiclass BufferAtomicPat<string OpPrefix, ValueType vt, string Inst> {
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} // end foreach RtnMode
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}
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multiclass BufferAtomicCmpSwapPat<ValueType vt, ValueType data_vt, string Inst> {
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foreach RtnMode = ["ret", "noret"] in {
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defvar Op = !cast<SDPatternOperator>("AMDGPUatomic_cmp_swap_global_" # RtnMode
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# "_" # vt.Size);
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defvar InstSuffix = !if(!eq(RtnMode, "ret"), "_RTN", "");
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defvar OffsetResDag = (!cast<MUBUF_Pseudo>(Inst # "_OFFSET" # InstSuffix)
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getVregSrcForVT<data_vt>.ret:$vdata_in, SReg_128:$srsrc, SCSrc_b32:$soffset,
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offset:$offset);
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def : Pat<
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(vt (Op (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset), data_vt:$vdata_in)),
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!if(!eq(RtnMode, "ret"),
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(EXTRACT_SUBREG OffsetResDag, !if(!eq(vt, i32), sub0, sub0_sub1)),
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OffsetResDag)
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>;
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defvar Addr64ResDag = (!cast<MUBUF_Pseudo>(Inst # "_ADDR64" # InstSuffix)
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getVregSrcForVT<data_vt>.ret:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc,
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SCSrc_b32:$soffset, offset:$offset);
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def : Pat<
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(vt (Op (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset),
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data_vt:$vdata_in)),
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!if(!eq(RtnMode, "ret"),
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(EXTRACT_SUBREG Addr64ResDag, !if(!eq(vt, i32), sub0, sub0_sub1)),
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Addr64ResDag)
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>;
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} // end foreach RtnMode
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}
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foreach Ty = [i32, i64] in {
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defvar Suffix = !if(!eq(Ty, i64), "_X2", "");
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@ -1418,6 +1449,9 @@ defm : BufferAtomicPat<"atomic_dec_global", Ty, "BUFFER_ATOMIC_DEC" # Suffix>;
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} // end foreach Ty
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defm : BufferAtomicCmpSwapPat<i32, v2i32, "BUFFER_ATOMIC_CMPSWAP">;
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defm : BufferAtomicCmpSwapPat<i64, v2i64, "BUFFER_ATOMIC_CMPSWAP_X2">;
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multiclass SIBufferAtomicPat<string OpPrefix, ValueType vt, string Inst,
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list<string> RtnModes = ["ret", "noret"]> {
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foreach RtnMode = RtnModes in {
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@ -28,7 +28,7 @@ body: |
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; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
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; GFX6-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
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; GFX6-NEXT: [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 0, 1, implicit $exec :: (load store seq_cst (s32), addrspace 1)
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; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
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; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
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; GFX6-NEXT: $vgpr0 = COPY [[COPY3]]
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; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s32_global
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; GFX7: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
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@ -43,7 +43,7 @@ body: |
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; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
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; GFX7-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
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; GFX7-NEXT: [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 0, 1, implicit $exec :: (load store seq_cst (s32), addrspace 1)
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; GFX7-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
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; GFX7-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
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; GFX7-NEXT: $vgpr0 = COPY [[COPY3]]
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; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s32_global
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; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
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@ -112,7 +112,7 @@ body: |
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; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
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; GFX6-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
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; GFX6-NEXT: [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 4, 1, implicit $exec :: (load store seq_cst (s32), addrspace 1)
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; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
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; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
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; GFX6-NEXT: $vgpr0 = COPY [[COPY3]]
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; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_gep4
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; GFX7: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
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@ -127,7 +127,7 @@ body: |
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; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
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; GFX7-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
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; GFX7-NEXT: [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 4, 1, implicit $exec :: (load store seq_cst (s32), addrspace 1)
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; GFX7-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
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; GFX7-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
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; GFX7-NEXT: $vgpr0 = COPY [[COPY3]]
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; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_gep4
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; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
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@ -218,7 +218,7 @@ body: |
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; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
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; GFX6-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
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; GFX6-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 0, 1, implicit $exec :: (load store seq_cst (s64), addrspace 1)
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; GFX6-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
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; GFX6-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
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; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[COPY3]]
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; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s64_global
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; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
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@ -233,7 +233,7 @@ body: |
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; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
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; GFX7-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
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; GFX7-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 0, 1, implicit $exec :: (load store seq_cst (s64), addrspace 1)
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; GFX7-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
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; GFX7-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
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; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[COPY3]]
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; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s64_global
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; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
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@ -302,7 +302,7 @@ body: |
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; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
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; GFX6-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
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; GFX6-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 4, 1, implicit $exec :: (load store seq_cst (s64), addrspace 1)
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; GFX6-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
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; GFX6-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
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; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[COPY3]]
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; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s64_global_gep4
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; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
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@ -317,7 +317,7 @@ body: |
|
||||
; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||
; GFX7-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||
; GFX7-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 4, 1, implicit $exec :: (load store seq_cst (s64), addrspace 1)
|
||||
; GFX7-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
|
||||
; GFX7-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
|
||||
; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[COPY3]]
|
||||
; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s64_global_gep4
|
||||
; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||
@ -418,7 +418,7 @@ body: |
|
||||
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||
; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE3]], %subreg.sub2_sub3
|
||||
; GFX6-NEXT: [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE4]], 0, 0, 1, implicit $exec :: (load store seq_cst (s32), addrspace 1)
|
||||
; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
|
||||
; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
|
||||
; GFX6-NEXT: $vgpr0 = COPY [[COPY7]]
|
||||
; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_gepm4
|
||||
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||
@ -443,7 +443,7 @@ body: |
|
||||
; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||
; GFX7-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE3]], %subreg.sub2_sub3
|
||||
; GFX7-NEXT: [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE4]], 0, 0, 1, implicit $exec :: (load store seq_cst (s32), addrspace 1)
|
||||
; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
|
||||
; GFX7-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
|
||||
; GFX7-NEXT: $vgpr0 = COPY [[COPY7]]
|
||||
; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_gepm4
|
||||
; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||
@ -534,7 +534,7 @@ body: |
|
||||
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||
; GFX6-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||
; GFX6-NEXT: [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 0, 1, implicit $exec :: (load store seq_cst (s32), addrspace 1)
|
||||
; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
|
||||
; GFX6-NEXT: [[COPY3:%[0-9]+]]:av_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
|
||||
; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_nortn
|
||||
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||
; GFX7-NEXT: {{ $}}
|
||||
@ -548,7 +548,7 @@ body: |
|
||||
; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||
; GFX7-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||
; GFX7-NEXT: [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 0, 1, implicit $exec :: (load store seq_cst (s32), addrspace 1)
|
||||
; GFX7-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
|
||||
; GFX7-NEXT: [[COPY3:%[0-9]+]]:av_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN]].sub0
|
||||
; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_nortn
|
||||
; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
|
||||
; GFX7-FLAT-NEXT: {{ $}}
|
||||
@ -611,7 +611,7 @@ body: |
|
||||
; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||
; GFX6-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||
; GFX6-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 0, 1, implicit $exec :: (load store seq_cst (s64), addrspace 1)
|
||||
; GFX6-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
|
||||
; GFX6-NEXT: [[COPY3:%[0-9]+]]:av_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
|
||||
; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s64_global_nortn
|
||||
; GFX7: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||
; GFX7-NEXT: {{ $}}
|
||||
@ -625,7 +625,7 @@ body: |
|
||||
; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||
; GFX7-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||
; GFX7-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN [[REG_SEQUENCE]], [[COPY]], [[REG_SEQUENCE2]], 0, 0, 1, implicit $exec :: (load store seq_cst (s64), addrspace 1)
|
||||
; GFX7-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
|
||||
; GFX7-NEXT: [[COPY3:%[0-9]+]]:av_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN]].sub0_sub1
|
||||
; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s64_global_nortn
|
||||
; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
|
||||
; GFX7-FLAT-NEXT: {{ $}}
|
||||
@ -687,7 +687,7 @@ body: |
|
||||
; GFX6-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||
; GFX6-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||
; GFX6-NEXT: [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], 0, 0, 1, implicit $exec :: (load store seq_cst (s32), addrspace 1)
|
||||
; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN]].sub0
|
||||
; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN]].sub0
|
||||
; GFX6-NEXT: $vgpr0 = COPY [[COPY3]]
|
||||
; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr
|
||||
; GFX7: liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||
@ -701,7 +701,7 @@ body: |
|
||||
; GFX7-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||
; GFX7-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||
; GFX7-NEXT: [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], 0, 0, 1, implicit $exec :: (load store seq_cst (s32), addrspace 1)
|
||||
; GFX7-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN]].sub0
|
||||
; GFX7-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN]].sub0
|
||||
; GFX7-NEXT: $vgpr0 = COPY [[COPY3]]
|
||||
; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr
|
||||
; GFX7-FLAT: liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||
@ -773,7 +773,7 @@ body: |
|
||||
; GFX6-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||
; GFX6-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||
; GFX6-NEXT: [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], 0, 4095, 1, implicit $exec :: (load store seq_cst (s32), addrspace 1)
|
||||
; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN]].sub0
|
||||
; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN]].sub0
|
||||
; GFX6-NEXT: $vgpr0 = COPY [[COPY3]]
|
||||
; GFX7-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr_offset_4095
|
||||
; GFX7: liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||
@ -787,7 +787,7 @@ body: |
|
||||
; GFX7-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
|
||||
; GFX7-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3
|
||||
; GFX7-NEXT: [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], 0, 4095, 1, implicit $exec :: (load store seq_cst (s32), addrspace 1)
|
||||
; GFX7-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN]].sub0
|
||||
; GFX7-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN]].sub0
|
||||
; GFX7-NEXT: $vgpr0 = COPY [[COPY3]]
|
||||
; GFX7-FLAT-LABEL: name: amdgpu_atomic_cmpxchg_s32_global_sgpr_ptr_offset_4095
|
||||
; GFX7-FLAT: liveins: $sgpr0_sgpr1, $vgpr2, $vgpr3
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user