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[llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands.

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This patch makes it so that cases where multiple instructions that
differ only in their ConstantInt or ConstantFP MachineOperand values no
longer collide. For instance:

%0:_(s1) = G_CONSTANT i1 true
%1:_(s1) = G_CONSTANT i1 false
%2:_(s32) = G_FCONSTANT float 1.0
%3:_(s32) = G_FCONSTANT float 0.0

Prior to this patch the first two instructions would collide together.
Also, the last two G_FCONSTANT instructions would also collide. Now they
will no longer collide.

Differential Revision: https://reviews.llvm.org/D71558
This commit is contained in:
Puyan Lotfi 2019-12-16 13:23:03 -05:00
parent aa5ee8f244
commit f63b64c0c3
2 changed files with 21 additions and 2 deletions
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9
llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
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@ -53,6 +53,13 @@ std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
// Gets a hashable artifact from a given MachineOperand (ie an unsigned).
auto GetHashableMO = [this](const MachineOperand &MO) -> unsigned {
switch (MO.getType()) {
case MachineOperand::MO_CImmediate:
return hash_combine(MO.getType(), MO.getTargetFlags(),
MO.getCImm()->getZExtValue());
case MachineOperand::MO_FPImmediate:
return hash_combine(
MO.getType(), MO.getTargetFlags(),
MO.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue());
case MachineOperand::MO_Immediate:
return MO.getImm();
case MachineOperand::MO_TargetIndex:
@ -70,8 +77,6 @@ std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
// TODO: Handle the following Immediate/Index/ID/Predicate cases. They can
// be hashed on in a stable manner.
case MachineOperand::MO_CImmediate:
case MachineOperand::MO_FPImmediate:
case MachineOperand::MO_FrameIndex:
case MachineOperand::MO_ConstantPoolIndex:
case MachineOperand::MO_JumpTableIndex:

14
llvm/test/CodeGen/MIR/Generic/CFPImmMIRCanonHash.mir Normal file
View File

@ -0,0 +1,14 @@
# RUN: llc -run-pass mir-canonicalizer -o - %s | FileCheck %s
---
name: cimm_fpimm_hash_test
body: |
bb.0:
; CHECK: _1:_(s1) = G_CONSTANT i1 true
; CHECK: _1:_(s1) = G_CONSTANT i1 false
; CHECK: _1:_(s32) = G_FCONSTANT float
; CHECK: _1:_(s32) = G_FCONSTANT float
%0:_(s1) = G_CONSTANT i1 true
%1:_(s1) = G_CONSTANT i1 false
%2:_(s32) = G_FCONSTANT float 1.0
%3:_(s32) = G_FCONSTANT float 0.0
...