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[LegalizeVectorOps] Improve handling of multi-result operations.
This system wasn't very well designed for multi-result nodes. As a consequence they weren't consistently registered in the LegalizedNodes map leading to nodes being revisited for different results. I've removed the "Result" variable from the main LegalizeOp method and used a SDNode* instead. The result number from the incoming Op SDValue is only used for deciding which result to return to the caller. When LegalizeOp is called it should always register a legalized result for all of its results. Future calls for any other result should be pulled for the LegalizedNodes map. Legal nodes will now register all of their results in the map instead of just the one we were called for. The Expand and Promote handling to use a vector of results similar to LegalizeDAG. Each of the new results is then re-legalized and logged in the LegalizedNodes map for all of the Results for the node being legalized. None of the handles register their own results now. And none call ReplaceAllUsesOfValueWith now. Custom handling now always passes result number 0 to LowerOperation. This matches what LegalizeDAG does. Since the introduction of STRICT nodes, I've encountered several issues with X86's custom handling being called with an SDValue pointing at the chain and our custom handlers using that to get a VT instead of result 0. This should prevent us from having any more of those issues. On return we will update the LegalizedNodes map for all results so we shouldn't call the custom handler again for each result number. I want to push SDNode* further into the Expand and Promote handlers, but I've left that for a follow to keep this patch size down. I've created a dummy SDValue(Node, 0) to keep the handlers working. Differential Revision: https://reviews.llvm.org/D72224
This commit is contained in:
Craig Topper
parent
2d077d6dfa
commit
f678fc7660
@ -75,7 +75,17 @@ class VectorLegalizer {
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SDValue LegalizeOp(SDValue Op);
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/// Assuming the node is legal, "legalize" the results.
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SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
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SDValue TranslateLegalizeResults(SDValue Op, SDNode *Result);
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/// Make sure Results are legal and update the translation cache.
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SDValue RecursivelyLegalizeResults(SDValue Op,
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MutableArrayRef<SDValue> Results);
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/// Wrapper to interface LowerOperation with a vector of Results.
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/// Returns false if the target wants to use default expansion. Otherwise
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/// returns true. If return is true and the Results are empty, then the
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/// target wants to keep the input node as is.
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bool LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results);
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/// Implements unrolling a VSETCC.
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SDValue UnrollVSETCC(SDValue Op);
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@ -84,15 +94,15 @@ class VectorLegalizer {
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///
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/// This is just a high-level routine to dispatch to specific code paths for
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/// operations to legalize them.
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SDValue Expand(SDValue Op);
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void Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results);
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/// Implements expansion for FP_TO_UINT; falls back to UnrollVectorOp if
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/// FP_TO_SINT isn't legal.
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SDValue ExpandFP_TO_UINT(SDValue Op);
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void ExpandFP_TO_UINT(SDValue Op, SmallVectorImpl<SDValue> &Results);
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/// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
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/// SINT_TO_FLOAT and SHR on vectors isn't legal.
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SDValue ExpandUINT_TO_FLOAT(SDValue Op);
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void ExpandUINT_TO_FLOAT(SDValue Op, SmallVectorImpl<SDValue> &Results);
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/// Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
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SDValue ExpandSEXTINREG(SDValue Op);
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@ -130,8 +140,8 @@ class VectorLegalizer {
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/// supported by the target.
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SDValue ExpandVSELECT(SDValue Op);
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SDValue ExpandSELECT(SDValue Op);
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std::pair<SDValue, SDValue> ExpandLoad(SDValue Op);
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SDValue ExpandStore(SDValue Op);
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std::pair<SDValue, SDValue> ExpandLoad(SDNode *N);
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SDValue ExpandStore(SDNode *N);
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SDValue ExpandFNEG(SDValue Op);
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SDValue ExpandFSUB(SDValue Op);
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SDValue ExpandBITREVERSE(SDValue Op);
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@ -141,32 +151,33 @@ class VectorLegalizer {
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SDValue ExpandFunnelShift(SDValue Op);
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SDValue ExpandROT(SDValue Op);
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SDValue ExpandFMINNUM_FMAXNUM(SDValue Op);
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SDValue ExpandUADDSUBO(SDValue Op);
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SDValue ExpandSADDSUBO(SDValue Op);
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SDValue ExpandMULO(SDValue Op);
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void ExpandUADDSUBO(SDValue Op, SmallVectorImpl<SDValue> &Results);
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void ExpandSADDSUBO(SDValue Op, SmallVectorImpl<SDValue> &Results);
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void ExpandMULO(SDValue Op, SmallVectorImpl<SDValue> &Results);
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SDValue ExpandAddSubSat(SDValue Op);
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SDValue ExpandFixedPointMul(SDValue Op);
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SDValue ExpandFixedPointDiv(SDValue Op);
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SDValue ExpandStrictFPOp(SDValue Op);
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void ExpandStrictFPOp(SDValue Op, SmallVectorImpl<SDValue> &Results);
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SDValue UnrollStrictFPOp(SDValue Op);
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void UnrollStrictFPOp(SDValue Op, SmallVectorImpl<SDValue> &Results);
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/// Implements vector promotion.
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///
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/// This is essentially just bitcasting the operands to a different type and
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/// bitcasting the result back to the original type.
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SDValue Promote(SDValue Op);
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void Promote(SDNode *Node, SmallVectorImpl<SDValue> &Results);
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/// Implements [SU]INT_TO_FP vector promotion.
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///
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/// This is a [zs]ext of the input operand to a larger integer type.
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SDValue PromoteINT_TO_FP(SDValue Op);
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void PromoteINT_TO_FP(SDValue Op, SmallVectorImpl<SDValue> &Results);
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/// Implements FP_TO_[SU]INT vector promotion of the result type.
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///
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/// It is promoted to a larger integer type. The result is then
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/// truncated back to the original type.
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SDValue PromoteFP_TO_INT(SDValue Op);
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void PromoteFP_TO_INT(SDValue Op, SmallVectorImpl<SDValue> &Results);
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public:
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VectorLegalizer(SelectionDAG& dag) :
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@ -222,11 +233,27 @@ bool VectorLegalizer::Run() {
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return Changed;
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}
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SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
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SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDNode *Result) {
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assert(Op->getNumValues() == Result->getNumValues() &&
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"Unexpected number of results");
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// Generic legalization: just pass the operand through.
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for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
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AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
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return Result.getValue(Op.getResNo());
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for (unsigned i = 0, e = Op->getNumValues(); i != e; ++i)
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AddLegalizedOperand(Op.getValue(i), SDValue(Result, i));
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return SDValue(Result, Op.getResNo());
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}
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SDValue
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VectorLegalizer::RecursivelyLegalizeResults(SDValue Op,
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MutableArrayRef<SDValue> Results) {
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assert(Results.size() == Op->getNumValues() &&
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"Unexpected number of results");
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// Make sure that the generated code is itself legal.
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for (unsigned i = 0, e = Results.size(); i != e; ++i) {
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Results[i] = LegalizeOp(Results[i]);
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AddLegalizedOperand(Op.getValue(i), Results[i]);
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}
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return Results[Op.getResNo()];
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}
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SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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@ -235,18 +262,15 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
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if (I != LegalizedNodes.end()) return I->second;
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SDNode* Node = Op.getNode();
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// Legalize the operands
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SmallVector<SDValue, 8> Ops;
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for (const SDValue &Op : Node->op_values())
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Ops.push_back(LegalizeOp(Op));
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for (const SDValue &Oper : Op->op_values())
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Ops.push_back(LegalizeOp(Oper));
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SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops),
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Op.getResNo());
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SDNode *Node = DAG.UpdateNodeOperands(Op.getNode(), Ops);
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if (Op.getOpcode() == ISD::LOAD) {
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LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
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LoadSDNode *LD = cast<LoadSDNode>(Node);
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ISD::LoadExtType ExtType = LD->getExtensionType();
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if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
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LLVM_DEBUG(dbgs() << "\nLegalizing extending vector load: ";
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@ -255,22 +279,21 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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LD->getMemoryVT())) {
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default: llvm_unreachable("This action is not supported yet!");
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case TargetLowering::Legal:
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return TranslateLegalizeResults(Op, Result);
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case TargetLowering::Custom:
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if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
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assert(Lowered->getNumValues() == Op->getNumValues() &&
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"Unexpected number of results");
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if (Lowered != Result) {
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// Make sure the new code is also legal.
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Lowered = LegalizeOp(Lowered);
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Changed = true;
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}
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return TranslateLegalizeResults(Op, Lowered);
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return TranslateLegalizeResults(Op, Node);
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case TargetLowering::Custom: {
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SmallVector<SDValue, 2> ResultVals;
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if (LowerOperationWrapper(Node, ResultVals)) {
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if (ResultVals.empty())
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return TranslateLegalizeResults(Op, Node);
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Changed = true;
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return RecursivelyLegalizeResults(Op, ResultVals);
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}
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LLVM_FALLTHROUGH;
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}
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case TargetLowering::Expand: {
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Changed = true;
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std::pair<SDValue, SDValue> Tmp = ExpandLoad(Result);
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std::pair<SDValue, SDValue> Tmp = ExpandLoad(Node);
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AddLegalizedOperand(Op.getValue(0), Tmp.first);
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AddLegalizedOperand(Op.getValue(1), Tmp.second);
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return Op.getResNo() ? Tmp.first : Tmp.second;
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@ -278,7 +301,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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}
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}
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} else if (Op.getOpcode() == ISD::STORE) {
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StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
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StoreSDNode *ST = cast<StoreSDNode>(Node);
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EVT StVT = ST->getMemoryVT();
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MVT ValVT = ST->getValue().getSimpleValueType();
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if (StVT.isVector() && ST->isTruncatingStore()) {
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@ -287,19 +310,21 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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switch (TLI.getTruncStoreAction(ValVT, StVT)) {
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default: llvm_unreachable("This action is not supported yet!");
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case TargetLowering::Legal:
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return TranslateLegalizeResults(Op, Result);
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return TranslateLegalizeResults(Op, Node);
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case TargetLowering::Custom: {
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SDValue Lowered = TLI.LowerOperation(Result, DAG);
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if (Lowered != Result) {
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// Make sure the new code is also legal.
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Lowered = LegalizeOp(Lowered);
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SmallVector<SDValue, 1> ResultVals;
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if (LowerOperationWrapper(Node, ResultVals)) {
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if (ResultVals.empty())
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return TranslateLegalizeResults(Op, Node);
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Changed = true;
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return RecursivelyLegalizeResults(Op, ResultVals);
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}
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return TranslateLegalizeResults(Op, Lowered);
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LLVM_FALLTHROUGH;
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}
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case TargetLowering::Expand: {
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Changed = true;
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SDValue Chain = ExpandStore(Result);
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SDValue Chain = ExpandStore(Node);
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AddLegalizedOperand(Op, Chain);
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return Chain;
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}
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@ -310,17 +335,17 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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bool HasVectorValueOrOp = false;
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for (auto J = Node->value_begin(), E = Node->value_end(); J != E; ++J)
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HasVectorValueOrOp |= J->isVector();
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for (const SDValue &Op : Node->op_values())
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HasVectorValueOrOp |= Op.getValueType().isVector();
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for (const SDValue &Oper : Node->op_values())
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HasVectorValueOrOp |= Oper.getValueType().isVector();
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if (!HasVectorValueOrOp)
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return TranslateLegalizeResults(Op, Result);
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return TranslateLegalizeResults(Op, Node);
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TargetLowering::LegalizeAction Action = TargetLowering::Legal;
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EVT ValVT;
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switch (Op.getOpcode()) {
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default:
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return TranslateLegalizeResults(Op, Result);
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return TranslateLegalizeResults(Op, Node);
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#define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
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case ISD::STRICT_##DAGN:
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#include "llvm/IR/ConstrainedOps.def"
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@ -473,42 +498,70 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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LLVM_DEBUG(dbgs() << "\nLegalizing vector op: "; Node->dump(&DAG));
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SmallVector<SDValue, 8> ResultVals;
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switch (Action) {
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default: llvm_unreachable("This action is not supported yet!");
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case TargetLowering::Promote:
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Result = Promote(Op);
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Changed = true;
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LLVM_DEBUG(dbgs() << "Promoting\n");
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Promote(Node, ResultVals);
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assert(!ResultVals.empty() && "No results for promotion?");
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break;
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case TargetLowering::Legal:
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LLVM_DEBUG(dbgs() << "Legal node: nothing to do\n");
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break;
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case TargetLowering::Custom: {
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case TargetLowering::Custom:
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LLVM_DEBUG(dbgs() << "Trying custom legalization\n");
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if (SDValue Tmp1 = TLI.LowerOperation(Op, DAG)) {
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LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
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Result = Tmp1;
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if (LowerOperationWrapper(Node, ResultVals))
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break;
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}
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LLVM_DEBUG(dbgs() << "Could not custom legalize node\n");
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LLVM_FALLTHROUGH;
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}
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case TargetLowering::Expand:
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Result = Expand(Op);
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LLVM_DEBUG(dbgs() << "Expanding\n");
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Expand(Node, ResultVals);
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break;
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}
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// Make sure that the generated code is itself legal.
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if (Result != Op) {
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Result = LegalizeOp(Result);
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Changed = true;
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}
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if (ResultVals.empty())
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return TranslateLegalizeResults(Op, Node);
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// Note that LegalizeOp may be reentered even from single-use nodes, which
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// means that we always must cache transformed nodes.
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AddLegalizedOperand(Op, Result);
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return Result;
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Changed = true;
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return RecursivelyLegalizeResults(Op, ResultVals);
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}
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SDValue VectorLegalizer::Promote(SDValue Op) {
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// FIME: This is very similar to the X86 override of
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// TargetLowering::LowerOperationWrapper. Can we merge them somehow?
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bool VectorLegalizer::LowerOperationWrapper(SDNode *Node,
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SmallVectorImpl<SDValue> &Results) {
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SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
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if (!Res.getNode())
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return false;
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if (Res == SDValue(Node, 0))
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return true;
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// If the original node has one result, take the return value from
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// LowerOperation as is. It might not be result number 0.
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if (Node->getNumValues() == 1) {
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Results.push_back(Res);
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return true;
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}
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// If the original node has multiple results, then the return node should
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// have the same number of results.
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assert((Node->getNumValues() == Res->getNumValues()) &&
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"Lowering returned the wrong number of results!");
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// Places new result values base on N result number.
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for (unsigned I = 0, E = Node->getNumValues(); I != E; ++I)
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Results.push_back(Res.getValue(I));
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return true;
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}
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void VectorLegalizer::Promote(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
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SDValue Op(Node, 0); // FIXME: Use Node throughout.
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// For a few operations there is a specific concept for promotion based on
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// the operand's type.
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switch (Op.getOpcode()) {
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@ -517,13 +570,15 @@ SDValue VectorLegalizer::Promote(SDValue Op) {
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case ISD::STRICT_SINT_TO_FP:
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case ISD::STRICT_UINT_TO_FP:
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// "Promote" the operation by extending the operand.
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return PromoteINT_TO_FP(Op);
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PromoteINT_TO_FP(Op, Results);
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return;
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case ISD::FP_TO_UINT:
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case ISD::FP_TO_SINT:
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case ISD::STRICT_FP_TO_UINT:
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case ISD::STRICT_FP_TO_SINT:
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// Promote the operation by extending the operand.
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return PromoteFP_TO_INT(Op);
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PromoteFP_TO_INT(Op, Results);
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return;
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case ISD::FP_ROUND:
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case ISD::FP_EXTEND:
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// These operations are used to do promotion so they can't be promoted
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@ -558,15 +613,20 @@ SDValue VectorLegalizer::Promote(SDValue Op) {
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}
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Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags());
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SDValue Res;
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if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
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(VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
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NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
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return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
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Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
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else
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return DAG.getNode(ISD::BITCAST, dl, VT, Op);
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Res = DAG.getNode(ISD::BITCAST, dl, VT, Op);
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Results.push_back(Res);
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}
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SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
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void VectorLegalizer::PromoteINT_TO_FP(SDValue Op,
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SmallVectorImpl<SDValue> &Results) {
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// INT_TO_FP operations may require the input operand be promoted even
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// when the type is otherwise legal.
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bool IsStrict = Op->isStrictFPOpcode();
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@ -589,18 +649,24 @@ SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
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Operands[j] = Op.getOperand(j);
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}
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if (IsStrict)
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return DAG.getNode(Op.getOpcode(), dl, {Op.getValueType(), MVT::Other},
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Operands);
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if (IsStrict) {
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SDValue Res = DAG.getNode(Op.getOpcode(), dl,
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{Op.getValueType(), MVT::Other}, Operands);
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Results.push_back(Res);
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Results.push_back(Res.getValue(1));
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return;
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}
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return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
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SDValue Res = DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
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Results.push_back(Res);
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}
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// For FP_TO_INT we promote the result type to a vector type with wider
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// elements and then truncate the result. This is different from the default
|
||||
// PromoteVector which uses bitcast to promote thus assumning that the
|
||||
// promoted vector type has the same overall size.
|
||||
SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op) {
|
||||
void VectorLegalizer::PromoteFP_TO_INT(SDValue Op,
|
||||
SmallVectorImpl<SDValue> &Results) {
|
||||
MVT VT = Op.getSimpleValueType();
|
||||
MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
|
||||
bool IsStrict = Op->isStrictFPOpcode();
|
||||
@ -639,14 +705,13 @@ SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op) {
|
||||
Promoted = DAG.getNode(NewOpc, dl, NVT, Promoted,
|
||||
DAG.getValueType(VT.getScalarType()));
|
||||
Promoted = DAG.getNode(ISD::TRUNCATE, dl, VT, Promoted);
|
||||
Results.push_back(Promoted);
|
||||
if (IsStrict)
|
||||
return DAG.getMergeValues({Promoted, Chain}, dl);
|
||||
|
||||
return Promoted;
|
||||
Results.push_back(Chain);
|
||||
}
|
||||
|
||||
std::pair<SDValue, SDValue> VectorLegalizer::ExpandLoad(SDValue Op) {
|
||||
LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
|
||||
std::pair<SDValue, SDValue> VectorLegalizer::ExpandLoad(SDNode *N) {
|
||||
LoadSDNode *LD = cast<LoadSDNode>(N);
|
||||
|
||||
EVT SrcVT = LD->getMemoryVT();
|
||||
EVT SrcEltVT = SrcVT.getScalarType();
|
||||
@ -655,7 +720,7 @@ std::pair<SDValue, SDValue> VectorLegalizer::ExpandLoad(SDValue Op) {
|
||||
SDValue NewChain;
|
||||
SDValue Value;
|
||||
if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
|
||||
SDLoc dl(Op);
|
||||
SDLoc dl(N);
|
||||
|
||||
SmallVector<SDValue, 8> Vals;
|
||||
SmallVector<SDValue, 8> LoadChains;
|
||||
@ -767,7 +832,7 @@ std::pair<SDValue, SDValue> VectorLegalizer::ExpandLoad(SDValue Op) {
|
||||
}
|
||||
|
||||
NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
|
||||
Value = DAG.getBuildVector(Op.getNode()->getValueType(0), dl, Vals);
|
||||
Value = DAG.getBuildVector(N->getValueType(0), dl, Vals);
|
||||
} else {
|
||||
std::tie(Value, NewChain) = TLI.scalarizeVectorLoad(LD, DAG);
|
||||
}
|
||||
@ -775,90 +840,122 @@ std::pair<SDValue, SDValue> VectorLegalizer::ExpandLoad(SDValue Op) {
|
||||
return std::make_pair(Value, NewChain);
|
||||
}
|
||||
|
||||
SDValue VectorLegalizer::ExpandStore(SDValue Op) {
|
||||
StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
|
||||
SDValue VectorLegalizer::ExpandStore(SDNode *N) {
|
||||
StoreSDNode *ST = cast<StoreSDNode>(N);
|
||||
SDValue TF = TLI.scalarizeVectorStore(ST, DAG);
|
||||
return TF;
|
||||
}
|
||||
|
||||
SDValue VectorLegalizer::Expand(SDValue Op) {
|
||||
void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
|
||||
SDValue Op(Node, 0); // FIXME: Just pass Node to all the expanders.
|
||||
|
||||
switch (Op->getOpcode()) {
|
||||
case ISD::SIGN_EXTEND_INREG:
|
||||
return ExpandSEXTINREG(Op);
|
||||
Results.push_back(ExpandSEXTINREG(Op));
|
||||
return;
|
||||
case ISD::ANY_EXTEND_VECTOR_INREG:
|
||||
return ExpandANY_EXTEND_VECTOR_INREG(Op);
|
||||
Results.push_back(ExpandANY_EXTEND_VECTOR_INREG(Op));
|
||||
return;
|
||||
case ISD::SIGN_EXTEND_VECTOR_INREG:
|
||||
return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
|
||||
Results.push_back(ExpandSIGN_EXTEND_VECTOR_INREG(Op));
|
||||
return;
|
||||
case ISD::ZERO_EXTEND_VECTOR_INREG:
|
||||
return ExpandZERO_EXTEND_VECTOR_INREG(Op);
|
||||
Results.push_back(ExpandZERO_EXTEND_VECTOR_INREG(Op));
|
||||
return;
|
||||
case ISD::BSWAP:
|
||||
return ExpandBSWAP(Op);
|
||||
Results.push_back(ExpandBSWAP(Op));
|
||||
return;
|
||||
case ISD::VSELECT:
|
||||
return ExpandVSELECT(Op);
|
||||
Results.push_back(ExpandVSELECT(Op));
|
||||
return;
|
||||
case ISD::SELECT:
|
||||
return ExpandSELECT(Op);
|
||||
Results.push_back(ExpandSELECT(Op));
|
||||
return;
|
||||
case ISD::FP_TO_UINT:
|
||||
return ExpandFP_TO_UINT(Op);
|
||||
ExpandFP_TO_UINT(Op, Results);
|
||||
return;
|
||||
case ISD::UINT_TO_FP:
|
||||
return ExpandUINT_TO_FLOAT(Op);
|
||||
ExpandUINT_TO_FLOAT(Op, Results);
|
||||
return;
|
||||
case ISD::FNEG:
|
||||
return ExpandFNEG(Op);
|
||||
Results.push_back(ExpandFNEG(Op));
|
||||
return;
|
||||
case ISD::FSUB:
|
||||
return ExpandFSUB(Op);
|
||||
if (SDValue Tmp = ExpandFSUB(Op))
|
||||
Results.push_back(Tmp);
|
||||
return;
|
||||
case ISD::SETCC:
|
||||
return UnrollVSETCC(Op);
|
||||
Results.push_back(UnrollVSETCC(Op));
|
||||
return;
|
||||
case ISD::ABS:
|
||||
return ExpandABS(Op);
|
||||
Results.push_back(ExpandABS(Op));
|
||||
return;
|
||||
case ISD::BITREVERSE:
|
||||
return ExpandBITREVERSE(Op);
|
||||
if (SDValue Tmp = ExpandBITREVERSE(Op))
|
||||
Results.push_back(Tmp);
|
||||
return;
|
||||
case ISD::CTPOP:
|
||||
return ExpandCTPOP(Op);
|
||||
Results.push_back(ExpandCTPOP(Op));
|
||||
return;
|
||||
case ISD::CTLZ:
|
||||
case ISD::CTLZ_ZERO_UNDEF:
|
||||
return ExpandCTLZ(Op);
|
||||
Results.push_back(ExpandCTLZ(Op));
|
||||
return;
|
||||
case ISD::CTTZ:
|
||||
case ISD::CTTZ_ZERO_UNDEF:
|
||||
return ExpandCTTZ(Op);
|
||||
Results.push_back(ExpandCTTZ(Op));
|
||||
return;
|
||||
case ISD::FSHL:
|
||||
case ISD::FSHR:
|
||||
return ExpandFunnelShift(Op);
|
||||
Results.push_back(ExpandFunnelShift(Op));
|
||||
return;
|
||||
case ISD::ROTL:
|
||||
case ISD::ROTR:
|
||||
return ExpandROT(Op);
|
||||
Results.push_back(ExpandROT(Op));
|
||||
return;
|
||||
case ISD::FMINNUM:
|
||||
case ISD::FMAXNUM:
|
||||
return ExpandFMINNUM_FMAXNUM(Op);
|
||||
Results.push_back(ExpandFMINNUM_FMAXNUM(Op));
|
||||
return;
|
||||
case ISD::UADDO:
|
||||
case ISD::USUBO:
|
||||
return ExpandUADDSUBO(Op);
|
||||
ExpandUADDSUBO(Op, Results);
|
||||
return;
|
||||
case ISD::SADDO:
|
||||
case ISD::SSUBO:
|
||||
return ExpandSADDSUBO(Op);
|
||||
ExpandSADDSUBO(Op, Results);
|
||||
return;
|
||||
case ISD::UMULO:
|
||||
case ISD::SMULO:
|
||||
return ExpandMULO(Op);
|
||||
ExpandMULO(Op, Results);
|
||||
return;
|
||||
case ISD::USUBSAT:
|
||||
case ISD::SSUBSAT:
|
||||
case ISD::UADDSAT:
|
||||
case ISD::SADDSAT:
|
||||
return ExpandAddSubSat(Op);
|
||||
Results.push_back(ExpandAddSubSat(Op));
|
||||
return;
|
||||
case ISD::SMULFIX:
|
||||
case ISD::UMULFIX:
|
||||
return ExpandFixedPointMul(Op);
|
||||
Results.push_back(ExpandFixedPointMul(Op));
|
||||
return;
|
||||
case ISD::SMULFIXSAT:
|
||||
case ISD::UMULFIXSAT:
|
||||
// FIXME: We do not expand SMULFIXSAT/UMULFIXSAT here yet, not sure exactly
|
||||
// why. Maybe it results in worse codegen compared to the unroll for some
|
||||
// targets? This should probably be investigated. And if we still prefer to
|
||||
// unroll an explanation could be helpful.
|
||||
return DAG.UnrollVectorOp(Op.getNode());
|
||||
Results.push_back(DAG.UnrollVectorOp(Op.getNode()));
|
||||
return;
|
||||
case ISD::SDIVFIX:
|
||||
case ISD::UDIVFIX:
|
||||
return ExpandFixedPointDiv(Op);
|
||||
Results.push_back(ExpandFixedPointDiv(Op));
|
||||
return;
|
||||
#define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
|
||||
case ISD::STRICT_##DAGN:
|
||||
#include "llvm/IR/ConstrainedOps.def"
|
||||
return ExpandStrictFPOp(Op);
|
||||
ExpandStrictFPOp(Op, Results);
|
||||
return;
|
||||
case ISD::VECREDUCE_ADD:
|
||||
case ISD::VECREDUCE_MUL:
|
||||
case ISD::VECREDUCE_AND:
|
||||
@ -872,9 +969,11 @@ SDValue VectorLegalizer::Expand(SDValue Op) {
|
||||
case ISD::VECREDUCE_FMUL:
|
||||
case ISD::VECREDUCE_FMAX:
|
||||
case ISD::VECREDUCE_FMIN:
|
||||
return TLI.expandVecReduce(Op.getNode(), DAG);
|
||||
Results.push_back(TLI.expandVecReduce(Op.getNode(), DAG));
|
||||
return;
|
||||
default:
|
||||
return DAG.UnrollVectorOp(Op.getNode());
|
||||
Results.push_back(DAG.UnrollVectorOp(Op.getNode()));
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1120,7 +1219,7 @@ SDValue VectorLegalizer::ExpandBITREVERSE(SDValue Op) {
|
||||
return DAG.UnrollVectorOp(Op.getNode());
|
||||
|
||||
// Let LegalizeDAG handle this later.
|
||||
return Op;
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
|
||||
@ -1180,23 +1279,28 @@ SDValue VectorLegalizer::ExpandABS(SDValue Op) {
|
||||
return DAG.UnrollVectorOp(Op.getNode());
|
||||
}
|
||||
|
||||
SDValue VectorLegalizer::ExpandFP_TO_UINT(SDValue Op) {
|
||||
void VectorLegalizer::ExpandFP_TO_UINT(SDValue Op,
|
||||
SmallVectorImpl<SDValue> &Results) {
|
||||
// Attempt to expand using TargetLowering.
|
||||
SDValue Result, Chain;
|
||||
if (TLI.expandFP_TO_UINT(Op.getNode(), Result, Chain, DAG)) {
|
||||
Results.push_back(Result);
|
||||
if (Op->isStrictFPOpcode())
|
||||
// Relink the chain
|
||||
DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Chain);
|
||||
return Result;
|
||||
Results.push_back(Chain);
|
||||
return;
|
||||
}
|
||||
|
||||
// Otherwise go ahead and unroll.
|
||||
if (Op->isStrictFPOpcode())
|
||||
return UnrollStrictFPOp(Op);
|
||||
return DAG.UnrollVectorOp(Op.getNode());
|
||||
if (Op->isStrictFPOpcode()) {
|
||||
UnrollStrictFPOp(Op, Results);
|
||||
return;
|
||||
}
|
||||
|
||||
Results.push_back(DAG.UnrollVectorOp(Op.getNode()));
|
||||
}
|
||||
|
||||
SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
|
||||
void VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op,
|
||||
SmallVectorImpl<SDValue> &Results) {
|
||||
bool IsStrict = Op.getNode()->isStrictFPOpcode();
|
||||
unsigned OpNo = IsStrict ? 1 : 0;
|
||||
SDValue Src = Op.getOperand(OpNo);
|
||||
@ -1207,10 +1311,10 @@ SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
|
||||
SDValue Result;
|
||||
SDValue Chain;
|
||||
if (TLI.expandUINT_TO_FP(Op.getNode(), Result, Chain, DAG)) {
|
||||
Results.push_back(Result);
|
||||
if (IsStrict)
|
||||
// Relink the chain
|
||||
DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Chain);
|
||||
return Result;
|
||||
Results.push_back(Chain);
|
||||
return;
|
||||
}
|
||||
|
||||
// Make sure that the SINT_TO_FP and SRL instructions are available.
|
||||
@ -1219,9 +1323,13 @@ SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
|
||||
(IsStrict && TLI.getOperationAction(ISD::STRICT_SINT_TO_FP, VT) ==
|
||||
TargetLowering::Expand)) ||
|
||||
TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) {
|
||||
if (IsStrict)
|
||||
return UnrollStrictFPOp(Op);
|
||||
return DAG.UnrollVectorOp(Op.getNode());
|
||||
if (IsStrict) {
|
||||
UnrollStrictFPOp(Op, Results);
|
||||
return;
|
||||
}
|
||||
|
||||
Results.push_back(DAG.UnrollVectorOp(Op.getNode()));
|
||||
return;
|
||||
}
|
||||
|
||||
unsigned BW = VT.getScalarSizeInBits();
|
||||
@ -1261,9 +1369,9 @@ SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
|
||||
DAG.getNode(ISD::STRICT_FADD, DL, {Op.getValueType(), MVT::Other},
|
||||
{SDValue(fLO.getNode(), 1), fHI, fLO});
|
||||
|
||||
// Relink the chain
|
||||
DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), SDValue(Result.getNode(), 1));
|
||||
return Result;
|
||||
Results.push_back(Result);
|
||||
Results.push_back(Result.getValue(1));
|
||||
return;
|
||||
}
|
||||
|
||||
// Convert hi and lo to floats
|
||||
@ -1274,7 +1382,7 @@ SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
|
||||
SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
|
||||
|
||||
// Add the two halves
|
||||
return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
|
||||
Results.push_back(DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO));
|
||||
}
|
||||
|
||||
SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
|
||||
@ -1295,7 +1403,7 @@ SDValue VectorLegalizer::ExpandFSUB(SDValue Op) {
|
||||
EVT VT = Op.getValueType();
|
||||
if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
|
||||
TLI.isOperationLegalOrCustom(ISD::FADD, VT))
|
||||
return Op; // Defer to LegalizeDAG
|
||||
return SDValue(); // Defer to LegalizeDAG
|
||||
|
||||
return DAG.UnrollVectorOp(Op.getNode());
|
||||
}
|
||||
@ -1346,44 +1454,30 @@ SDValue VectorLegalizer::ExpandFMINNUM_FMAXNUM(SDValue Op) {
|
||||
return DAG.UnrollVectorOp(Op.getNode());
|
||||
}
|
||||
|
||||
SDValue VectorLegalizer::ExpandUADDSUBO(SDValue Op) {
|
||||
void VectorLegalizer::ExpandUADDSUBO(SDValue Op,
|
||||
SmallVectorImpl<SDValue> &Results) {
|
||||
SDValue Result, Overflow;
|
||||
TLI.expandUADDSUBO(Op.getNode(), Result, Overflow, DAG);
|
||||
|
||||
if (Op.getResNo() == 0) {
|
||||
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Overflow));
|
||||
return Result;
|
||||
} else {
|
||||
AddLegalizedOperand(Op.getValue(0), LegalizeOp(Result));
|
||||
return Overflow;
|
||||
}
|
||||
Results.push_back(Result);
|
||||
Results.push_back(Overflow);
|
||||
}
|
||||
|
||||
SDValue VectorLegalizer::ExpandSADDSUBO(SDValue Op) {
|
||||
void VectorLegalizer::ExpandSADDSUBO(SDValue Op,
|
||||
SmallVectorImpl<SDValue> &Results) {
|
||||
SDValue Result, Overflow;
|
||||
TLI.expandSADDSUBO(Op.getNode(), Result, Overflow, DAG);
|
||||
|
||||
if (Op.getResNo() == 0) {
|
||||
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Overflow));
|
||||
return Result;
|
||||
} else {
|
||||
AddLegalizedOperand(Op.getValue(0), LegalizeOp(Result));
|
||||
return Overflow;
|
||||
}
|
||||
Results.push_back(Result);
|
||||
Results.push_back(Overflow);
|
||||
}
|
||||
|
||||
SDValue VectorLegalizer::ExpandMULO(SDValue Op) {
|
||||
void VectorLegalizer::ExpandMULO(SDValue Op,
|
||||
SmallVectorImpl<SDValue> &Results) {
|
||||
SDValue Result, Overflow;
|
||||
if (!TLI.expandMULO(Op.getNode(), Result, Overflow, DAG))
|
||||
std::tie(Result, Overflow) = DAG.UnrollVectorOverflowOp(Op.getNode());
|
||||
|
||||
if (Op.getResNo() == 0) {
|
||||
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Overflow));
|
||||
return Result;
|
||||
} else {
|
||||
AddLegalizedOperand(Op.getValue(0), LegalizeOp(Result));
|
||||
return Overflow;
|
||||
}
|
||||
Results.push_back(Result);
|
||||
Results.push_back(Overflow);
|
||||
}
|
||||
|
||||
SDValue VectorLegalizer::ExpandAddSubSat(SDValue Op) {
|
||||
@ -1406,16 +1500,22 @@ SDValue VectorLegalizer::ExpandFixedPointDiv(SDValue Op) {
|
||||
return DAG.UnrollVectorOp(N);
|
||||
}
|
||||
|
||||
SDValue VectorLegalizer::ExpandStrictFPOp(SDValue Op) {
|
||||
if (Op.getOpcode() == ISD::STRICT_UINT_TO_FP)
|
||||
return ExpandUINT_TO_FLOAT(Op);
|
||||
if (Op.getOpcode() == ISD::STRICT_FP_TO_UINT)
|
||||
return ExpandFP_TO_UINT(Op);
|
||||
void VectorLegalizer::ExpandStrictFPOp(SDValue Op,
|
||||
SmallVectorImpl<SDValue> &Results) {
|
||||
if (Op.getOpcode() == ISD::STRICT_UINT_TO_FP) {
|
||||
ExpandUINT_TO_FLOAT(Op, Results);
|
||||
return;
|
||||
}
|
||||
if (Op.getOpcode() == ISD::STRICT_FP_TO_UINT) {
|
||||
ExpandFP_TO_UINT(Op, Results);
|
||||
return;
|
||||
}
|
||||
|
||||
return UnrollStrictFPOp(Op);
|
||||
UnrollStrictFPOp(Op, Results);
|
||||
}
|
||||
|
||||
SDValue VectorLegalizer::UnrollStrictFPOp(SDValue Op) {
|
||||
void VectorLegalizer::UnrollStrictFPOp(SDValue Op,
|
||||
SmallVectorImpl<SDValue> &Results) {
|
||||
EVT VT = Op.getValue(0).getValueType();
|
||||
EVT EltVT = VT.getVectorElementType();
|
||||
unsigned NumElems = VT.getVectorNumElements();
|
||||
@ -1472,10 +1572,8 @@ SDValue VectorLegalizer::UnrollStrictFPOp(SDValue Op) {
|
||||
SDValue Result = DAG.getBuildVector(VT, dl, OpValues);
|
||||
SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OpChains);
|
||||
|
||||
AddLegalizedOperand(Op.getValue(0), Result);
|
||||
AddLegalizedOperand(Op.getValue(1), NewChain);
|
||||
|
||||
return Op.getResNo() ? NewChain : Result;
|
||||
Results.push_back(Result);
|
||||
Results.push_back(NewChain);
|
||||
}
|
||||
|
||||
SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
|
||||
|
||||
@ -181,3 +181,39 @@ if.then.i:
|
||||
if.end.i:
|
||||
ret i32 6
|
||||
}
|
||||
|
||||
; This test previously caused an infinite loop in legalize vector ops. Due to
|
||||
; CSE triggering on the call to UpdateNodeOperands and the resulting node not
|
||||
; being passed to LowerOperation. The add is needed to force the zext into a
|
||||
; sext on that path. The shuffle keeps the zext alive. The xor somehow
|
||||
; influences the zext to be visited before the sext exposing the CSE opportunity
|
||||
; for the sext since zext of setcc is custom legalized to a sext and shift.
|
||||
define <8 x i32> @legalize_loop(<8 x double> %arg) {
|
||||
; KNL-LABEL: legalize_loop:
|
||||
; KNL: ## %bb.0:
|
||||
; KNL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
|
||||
; KNL-NEXT: vcmpnltpd %zmm0, %zmm1, %k1
|
||||
; KNL-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
|
||||
; KNL-NEXT: vpsrld $31, %ymm0, %ymm1
|
||||
; KNL-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[3,2,1,0,7,6,5,4]
|
||||
; KNL-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,0,1]
|
||||
; KNL-NEXT: vpsubd %ymm0, %ymm1, %ymm0
|
||||
; KNL-NEXT: retq
|
||||
;
|
||||
; SKX-LABEL: legalize_loop:
|
||||
; SKX: ## %bb.0:
|
||||
; SKX-NEXT: vxorpd %xmm1, %xmm1, %xmm1
|
||||
; SKX-NEXT: vcmpnltpd %zmm0, %zmm1, %k0
|
||||
; SKX-NEXT: vpmovm2d %k0, %ymm0
|
||||
; SKX-NEXT: vpsrld $31, %ymm0, %ymm1
|
||||
; SKX-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[3,2,1,0,7,6,5,4]
|
||||
; SKX-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,0,1]
|
||||
; SKX-NEXT: vpsubd %ymm0, %ymm1, %ymm0
|
||||
; SKX-NEXT: retq
|
||||
%tmp = fcmp ogt <8 x double> %arg, zeroinitializer
|
||||
%tmp1 = xor <8 x i1> %tmp, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
|
||||
%tmp2 = zext <8 x i1> %tmp1 to <8 x i32>
|
||||
%tmp3 = shufflevector <8 x i32> %tmp2, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
|
||||
%tmp4 = add <8 x i32> %tmp2, %tmp3
|
||||
ret <8 x i32> %tmp4
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user