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[AArch64] add more tests for signbit math; NFC
llvm-svn: 338129
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@ -27,6 +27,20 @@ define i32 @add_zext_ifpos(i32 %x) {
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ret i32 %r
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}
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define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: add_zext_ifpos_vec_splat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
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; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: movi v1.4s, #41
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; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: ret
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%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = zext <4 x i1> %c to <4 x i32>
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%r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>
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ret <4 x i32> %r
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}
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define i32 @sel_ifpos_tval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifpos_tval_bigger:
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; CHECK: // %bb.0:
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@ -63,6 +77,20 @@ define i32 @add_sext_ifpos(i32 %x) {
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ret i32 %r
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}
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define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: add_sext_ifpos_vec_splat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
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; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: movi v1.4s, #42
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; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = sext <4 x i1> %c to <4 x i32>
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%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
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ret <4 x i32> %r
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}
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define i32 @sel_ifpos_fval_bigger(i32 %x) {
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; CHECK-LABEL: sel_ifpos_fval_bigger:
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; CHECK: // %bb.0:
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@ -145,3 +173,56 @@ define i32 @sel_ifneg_fval_bigger(i32 %x) {
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ret i32 %r
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}
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define i32 @add_lshr_not(i32 %x) {
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; CHECK-LABEL: add_lshr_not:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn w8, w0
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; CHECK-NEXT: lsr w8, w8, #31
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; CHECK-NEXT: add w0, w8, #41 // =41
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; CHECK-NEXT: ret
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%not = xor i32 %x, -1
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%sh = lshr i32 %not, 31
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%r = add i32 %sh, 41
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ret i32 %r
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}
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define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: add_lshr_not_vec_splat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn v0.16b, v0.16b
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; CHECK-NEXT: ushr v0.4s, v0.4s, #31
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; CHECK-NEXT: orr v0.4s, #42
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; CHECK-NEXT: ret
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%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
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%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
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ret <4 x i32> %r
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}
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define i32 @sub_lshr_not(i32 %x) {
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; CHECK-LABEL: sub_lshr_not:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn w8, w0
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; CHECK-NEXT: mov w9, #43
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; CHECK-NEXT: sub w0, w9, w8, lsr #31
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; CHECK-NEXT: ret
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%not = xor i32 %x, -1
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%sh = lshr i32 %not, 31
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%r = sub i32 43, %sh
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ret i32 %r
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}
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define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
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; CHECK-LABEL: sub_lshr_not_vec_splat:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn v0.16b, v0.16b
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; CHECK-NEXT: ushr v0.4s, v0.4s, #31
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; CHECK-NEXT: movi v1.4s, #42
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; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: ret
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%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
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%r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
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ret <4 x i32> %r
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}
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