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[RISCV] Merge RISCV::parseCPUKind and RISCV::checkCPUKind.

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Similar for RISCV::parseTuneCPU and RISCV::checkTuneCPUKind.

This makes the CPUKind enum no longer part of the API. It wasn't
providing much value. It was only used to pass between the two
functions.

By removing it, we can remove a dependency on a tablegen generated
file from the RISCVTargetParser.h file. Then we can remove a
dependency from several CMakeLists.txt.
This commit is contained in:
Craig Topper 2023-05-01 13:00:05 -07:00
parent 578a4716f5
commit fa42e7b6bc
8 changed files with 36 additions and 38 deletions
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1
clang/lib/Basic/CMakeLists.txt
View File

@ -125,7 +125,6 @@ add_clang_library(clangBasic
DEPENDS
omp_gen
RISCVTargetParserTableGen
)
target_link_libraries(clangBasic

5
clang/lib/Basic/Targets/RISCV.cpp
View File

@ -325,7 +325,7 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
bool RISCVTargetInfo::isValidCPUName(StringRef Name) const {
bool Is64Bit = getTriple().isArch64Bit();
return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name), Is64Bit);
return llvm::RISCV::parseCPU(Name, Is64Bit);
}
void RISCVTargetInfo::fillValidCPUList(
@ -336,8 +336,7 @@ void RISCVTargetInfo::fillValidCPUList(
bool RISCVTargetInfo::isValidTuneCPUName(StringRef Name) const {
bool Is64Bit = getTriple().isArch64Bit();
return llvm::RISCV::checkTuneCPUKind(
llvm::RISCV::parseTuneCPUKind(Name, Is64Bit), Is64Bit);
return llvm::RISCV::parseTuneCPU(Name, Is64Bit);
}
void RISCVTargetInfo::fillValidTuneCPUList(

1
clang/lib/Driver/CMakeLists.txt
View File

@ -95,7 +95,6 @@ add_clang_library(clangDriver
DEPENDS
ClangDriverOptions
RISCVTargetParserTableGen
LINK_LIBS
clangBasic

8
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
View File

@ -54,11 +54,11 @@ static void getRISCFeaturesFromMcpu(const Driver &D, const Arg *A,
StringRef Mcpu,
std::vector<StringRef> &Features) {
bool Is64Bit = Triple.isRISCV64();
llvm::RISCV::CPUKind CPUKind = llvm::RISCV::parseCPUKind(Mcpu);
if (!llvm::RISCV::checkCPUKind(CPUKind, Is64Bit)) {
if (!llvm::RISCV::parseCPU(Mcpu, Is64Bit)) {
// Try inverting Is64Bit in case the CPU is valid, but for the wrong target.
if (llvm::RISCV::checkCPUKind(CPUKind, !Is64Bit))
D.Diag(clang::diag::err_drv_invalid_riscv_cpu_name_for_target) << Mcpu << Is64Bit;
if (llvm::RISCV::parseCPU(Mcpu, !Is64Bit))
D.Diag(clang::diag::err_drv_invalid_riscv_cpu_name_for_target)
<< Mcpu << Is64Bit;
else
D.Diag(clang::diag::err_drv_unsupported_option_argument)
<< A->getSpelling() << Mcpu;

1
clang/lib/Sema/CMakeLists.txt
View File

@ -71,7 +71,6 @@ add_clang_library(clangSema
DEPENDS
ClangOpenCLBuiltinsImpl
omp_gen
RISCVTargetParserTableGen
LINK_LIBS
clangAST

4
llvm/docs/ReleaseNotes.rst
View File

@ -171,6 +171,10 @@ Changes to the RISC-V Backend
* Updated support experimental vector crypto extensions to version 0.5.1 of
the specification.
* Removed N extension (User-Level Interrupts) CSR names in the assembler.
* ``RISCV::parseCPUKind`` and ``RISCV::checkCPUKind`` were merged into a single
``RISCV::parseCPU``. The ``CPUKind`` enum is no longer part of the
RISCVTargetParser.h interface. Similar for ``parseTuneCPUkind`` and
``checkTuneCPUKind``.
Changes to the WebAssembly Backend
----------------------------------

12
llvm/include/llvm/TargetParser/RISCVTargetParser.h
View File

@ -26,16 +26,8 @@ namespace RISCV {
// We use 64 bits as the known part in the scalable vector types.
static constexpr unsigned RVVBitsPerBlock = 64;
enum CPUKind : unsigned {
#define PROC(ENUM, NAME, DEFAULT_MARCH) CK_##ENUM,
#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};
bool checkCPUKind(CPUKind Kind, bool IsRV64);
bool checkTuneCPUKind(CPUKind Kind, bool IsRV64);
CPUKind parseCPUKind(StringRef CPU);
CPUKind parseTuneCPUKind(StringRef CPU, bool IsRV64);
bool parseCPU(StringRef CPU, bool IsRV64);
bool parseTuneCPU(StringRef CPU, bool IsRV64);
StringRef getMArchFromMcpu(StringRef CPU);
void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);

42
llvm/lib/TargetParser/RISCVTargetParser.cpp
View File

@ -19,6 +19,12 @@
namespace llvm {
namespace RISCV {
enum CPUKind : unsigned {
#define PROC(ENUM, NAME, DEFAULT_MARCH) CK_##ENUM,
#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};
struct CPUInfo {
StringLiteral Name;
CPUKind Kind;
@ -33,13 +39,28 @@ constexpr CPUInfo RISCVCPUInfo[] = {
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};
bool checkCPUKind(CPUKind Kind, bool IsRV64) {
static CPUKind getCPUByName(StringRef CPU) {
return llvm::StringSwitch<CPUKind>(CPU)
#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
.Default(CK_INVALID);
}
bool parseCPU(StringRef CPU, bool IsRV64) {
CPUKind Kind = getCPUByName(CPU);
if (Kind == CK_INVALID)
return false;
return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
}
bool checkTuneCPUKind(CPUKind Kind, bool IsRV64) {
bool parseTuneCPU(StringRef TuneCPU, bool IsRV64) {
CPUKind Kind = llvm::StringSwitch<CPUKind>(TuneCPU)
#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
.Default(CK_INVALID);
if (Kind == CK_INVALID)
return false;
#define TUNE_PROC(ENUM, NAME) \
@ -49,23 +70,8 @@ bool checkTuneCPUKind(CPUKind Kind, bool IsRV64) {
return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
}
CPUKind parseCPUKind(StringRef CPU) {
return llvm::StringSwitch<CPUKind>(CPU)
#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
.Default(CK_INVALID);
}
CPUKind parseTuneCPUKind(StringRef TuneCPU, bool IsRV64) {
return llvm::StringSwitch<CPUKind>(TuneCPU)
#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
.Default(CK_INVALID);
}
StringRef getMArchFromMcpu(StringRef CPU) {
CPUKind Kind = parseCPUKind(CPU);
CPUKind Kind = getCPUByName(CPU);
return RISCVCPUInfo[static_cast<unsigned>(Kind)].DefaultMarch;
}