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[ARM] Lower sadd_sat to qadd8 and qadd16
Lower the target independent signed saturating intrinsics to qadd8 and qadd16. This custom lowers them from a sadd_sat, catching the node early before it is promoted. It also adds a QADD8b and QADD16b node to mean the bottom "lane" of a qadd8/qadd16, so that we can call demand bits on it to show that it does not use the upper bits. Also handles QSUB8 and QSUB16. Differential Revision: https://reviews.llvm.org/D68974 llvm-svn: 375402
This commit is contained in:
David Green
parent
5ba66fa53b
commit
fba831e791
@ -1021,6 +1021,12 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
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setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
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if (Subtarget->hasDSP()) {
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setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
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setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
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setOperationAction(ISD::SADDSAT, MVT::i16, Custom);
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setOperationAction(ISD::SSUBSAT, MVT::i16, Custom);
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}
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// i64 operation support.
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setOperationAction(ISD::MUL, MVT::i64, Expand);
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@ -1622,6 +1628,10 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::SMLSLDX: return "ARMISD::SMLSLDX";
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case ARMISD::SMMLAR: return "ARMISD::SMMLAR";
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case ARMISD::SMMLSR: return "ARMISD::SMMLSR";
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case ARMISD::QADD16b: return "ARMISD::QADD16b";
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case ARMISD::QSUB16b: return "ARMISD::QSUB16b";
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case ARMISD::QADD8b: return "ARMISD::QADD8b";
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case ARMISD::QSUB8b: return "ARMISD::QSUB8b";
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case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
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case ARMISD::BFI: return "ARMISD::BFI";
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case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
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@ -4445,6 +4455,35 @@ SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
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return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
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}
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static SDValue LowerSADDSUBSAT(SDValue Op, SelectionDAG &DAG,
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const ARMSubtarget *Subtarget) {
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EVT VT = Op.getValueType();
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if (!Subtarget->hasDSP())
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return SDValue();
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if (!VT.isSimple())
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return SDValue();
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unsigned NewOpcode;
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bool IsAdd = Op->getOpcode() == ISD::SADDSAT;
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switch (VT.getSimpleVT().SimpleTy) {
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default:
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return SDValue();
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case MVT::i8:
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NewOpcode = IsAdd ? ARMISD::QADD8b : ARMISD::QSUB8b;
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break;
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case MVT::i16:
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NewOpcode = IsAdd ? ARMISD::QADD16b : ARMISD::QSUB16b;
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break;
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}
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SDLoc dl(Op);
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SDValue Add =
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DAG.getNode(NewOpcode, dl, MVT::i32,
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DAG.getSExtOrTrunc(Op->getOperand(0), dl, MVT::i32),
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DAG.getSExtOrTrunc(Op->getOperand(1), dl, MVT::i32));
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return DAG.getNode(ISD::TRUNCATE, dl, VT, Add);
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}
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SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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SDValue Cond = Op.getOperand(0);
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SDValue SelectTrue = Op.getOperand(1);
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@ -9121,6 +9160,9 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::UADDO:
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case ISD::USUBO:
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return LowerUnsignedALUO(Op, DAG);
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case ISD::SADDSAT:
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case ISD::SSUBSAT:
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return LowerSADDSUBSAT(Op, DAG, Subtarget);
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case ISD::LOAD:
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return LowerPredicateLoad(Op, DAG);
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case ISD::STORE:
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@ -9205,6 +9247,10 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
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Results.push_back(Res.getValue(0));
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Results.push_back(Res.getValue(1));
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return;
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case ISD::SADDSAT:
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case ISD::SSUBSAT:
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Res = LowerSADDSUBSAT(SDValue(N, 0), DAG, Subtarget);
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break;
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case ISD::READCYCLECOUNTER:
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ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
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return;
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@ -14382,7 +14428,9 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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return SDValue();
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break;
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}
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case ARMISD::SMLALBB: {
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case ARMISD::SMLALBB:
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case ARMISD::QADD16b:
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case ARMISD::QSUB16b: {
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unsigned BitWidth = N->getValueType(0).getSizeInBits();
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APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 16);
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if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) ||
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@ -14418,6 +14466,15 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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return SDValue();
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break;
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}
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case ARMISD::QADD8b:
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case ARMISD::QSUB8b: {
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unsigned BitWidth = N->getValueType(0).getSizeInBits();
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APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 8);
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if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) ||
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(SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)))
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return SDValue();
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break;
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}
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case ISD::INTRINSIC_VOID:
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case ISD::INTRINSIC_W_CHAIN:
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switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
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@ -219,6 +219,12 @@ class VectorType;
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SMMLAR, // Signed multiply long, round and add
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SMMLSR, // Signed multiply long, subtract and round
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// Single Lane QADD8 and QADD16. Only the bottom lane. That's what the b stands for.
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QADD8b,
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QSUB8b,
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QADD16b,
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QSUB16b,
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// Operands of the standard BUILD_VECTOR node are not legalized, which
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// is fine if BUILD_VECTORs are always lowered to shuffles or other
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// operations, but for ARM some BUILD_VECTORs are legal as-is and their
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@ -238,6 +238,11 @@ def ARMsmlalbt : SDNode<"ARMISD::SMLALBT", SDT_LongMac, []>;
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def ARMsmlaltb : SDNode<"ARMISD::SMLALTB", SDT_LongMac, []>;
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def ARMsmlaltt : SDNode<"ARMISD::SMLALTT", SDT_LongMac, []>;
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def ARMqadd8b : SDNode<"ARMISD::QADD8b", SDT_ARMAnd, []>;
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def ARMqsub8b : SDNode<"ARMISD::QSUB8b", SDT_ARMAnd, []>;
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def ARMqadd16b : SDNode<"ARMISD::QADD16b", SDT_ARMAnd, []>;
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def ARMqsub16b : SDNode<"ARMISD::QSUB16b", SDT_ARMAnd, []>;
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// Vector operations shared between NEON and MVE
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def ARMvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
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@ -3750,6 +3755,15 @@ let DecoderMethod = "DecodeQADDInstruction" in
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[(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>;
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}
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def : ARMV6Pat<(ARMqadd8b rGPR:$Rm, rGPR:$Rn),
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(QADD8 rGPR:$Rm, rGPR:$Rn)>;
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def : ARMV6Pat<(ARMqsub8b rGPR:$Rm, rGPR:$Rn),
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(QSUB8 rGPR:$Rm, rGPR:$Rn)>;
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def : ARMV6Pat<(ARMqadd16b rGPR:$Rm, rGPR:$Rn),
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(QADD16 rGPR:$Rm, rGPR:$Rn)>;
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def : ARMV6Pat<(ARMqsub16b rGPR:$Rm, rGPR:$Rn),
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(QSUB16 rGPR:$Rm, rGPR:$Rn)>;
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def UQADD16 : AAIIntrinsic<0b01100110, 0b11110001, "uqadd16", int_arm_uqadd16>;
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def UQADD8 : AAIIntrinsic<0b01100110, 0b11111001, "uqadd8", int_arm_uqadd8>;
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def UQSUB16 : AAIIntrinsic<0b01100110, 0b11110111, "uqsub16", int_arm_uqsub16>;
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@ -2395,6 +2395,15 @@ def : Thumb2DSPPat<(int_arm_qadd(int_arm_qadd rGPR:$Rm, rGPR:$Rm), rGPR:$Rn),
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def : Thumb2DSPPat<(int_arm_qsub rGPR:$Rm, (int_arm_qadd rGPR:$Rn, rGPR:$Rn)),
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(t2QDSUB rGPR:$Rm, rGPR:$Rn)>;
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def : Thumb2DSPPat<(ARMqadd8b rGPR:$Rm, rGPR:$Rn),
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(t2QADD8 rGPR:$Rm, rGPR:$Rn)>;
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def : Thumb2DSPPat<(ARMqsub8b rGPR:$Rm, rGPR:$Rn),
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(t2QSUB8 rGPR:$Rm, rGPR:$Rn)>;
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def : Thumb2DSPPat<(ARMqadd16b rGPR:$Rm, rGPR:$Rn),
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(t2QADD16 rGPR:$Rm, rGPR:$Rn)>;
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def : Thumb2DSPPat<(ARMqsub16b rGPR:$Rm, rGPR:$Rn),
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(t2QSUB16 rGPR:$Rm, rGPR:$Rn)>;
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// Signed/Unsigned add/subtract
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def t2SASX : T2I_pam_intrinsics<0b010, 0b0000, "sasx", int_arm_sasx>;
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@ -233,35 +233,63 @@ define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
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; CHECK-T1-NEXT: .LCPI2_1:
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; CHECK-T1-NEXT: .long 4294934528 @ 0xffff8000
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;
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; CHECK-T2-LABEL: func16:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: add r0, r1
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; CHECK-T2-NEXT: movw r1, #32767
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; CHECK-T2-NEXT: cmp r0, r1
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; CHECK-T2-NEXT: it lt
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; CHECK-T2-NEXT: movlt r1, r0
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; CHECK-T2-NEXT: movw r0, #32768
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; CHECK-T2-NEXT: cmn.w r1, #32768
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; CHECK-T2-NEXT: movt r0, #65535
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; CHECK-T2-NEXT: it gt
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; CHECK-T2-NEXT: movgt r0, r1
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; CHECK-T2-NEXT: bx lr
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; CHECK-T2NODSP-LABEL: func16:
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; CHECK-T2NODSP: @ %bb.0:
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; CHECK-T2NODSP-NEXT: add r0, r1
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; CHECK-T2NODSP-NEXT: movw r1, #32767
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; CHECK-T2NODSP-NEXT: cmp r0, r1
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; CHECK-T2NODSP-NEXT: it lt
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; CHECK-T2NODSP-NEXT: movlt r1, r0
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; CHECK-T2NODSP-NEXT: movw r0, #32768
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; CHECK-T2NODSP-NEXT: cmn.w r1, #32768
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; CHECK-T2NODSP-NEXT: movt r0, #65535
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; CHECK-T2NODSP-NEXT: it gt
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; CHECK-T2NODSP-NEXT: movgt r0, r1
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; CHECK-T2NODSP-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: func16:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: add r0, r0, r1
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; CHECK-ARM-NEXT: mov r1, #255
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; CHECK-ARM-NEXT: orr r1, r1, #32512
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; CHECK-ARM-NEXT: cmp r0, r1
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; CHECK-ARM-NEXT: movlt r1, r0
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; CHECK-ARM-NEXT: ldr r0, .LCPI2_0
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; CHECK-ARM-NEXT: cmn r1, #32768
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; CHECK-ARM-NEXT: movgt r0, r1
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; CHECK-ARM-NEXT: bx lr
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; CHECK-ARM-NEXT: .p2align 2
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; CHECK-ARM-NEXT: @ %bb.1:
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; CHECK-ARM-NEXT: .LCPI2_0:
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; CHECK-ARM-NEXT: .long 4294934528 @ 0xffff8000
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; CHECK-T2DSP-LABEL: func16:
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; CHECK-T2DSP: @ %bb.0:
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; CHECK-T2DSP-NEXT: qadd16 r0, r0, r1
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; CHECK-T2DSP-NEXT: sxth r0, r0
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; CHECK-T2DSP-NEXT: bx lr
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;
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; CHECK-ARMNODPS-LABEL: func16:
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; CHECK-ARMNODPS: @ %bb.0:
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; CHECK-ARMNODPS-NEXT: add r0, r0, r1
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; CHECK-ARMNODPS-NEXT: mov r1, #255
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; CHECK-ARMNODPS-NEXT: orr r1, r1, #32512
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; CHECK-ARMNODPS-NEXT: cmp r0, r1
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; CHECK-ARMNODPS-NEXT: movlt r1, r0
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; CHECK-ARMNODPS-NEXT: ldr r0, .LCPI2_0
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; CHECK-ARMNODPS-NEXT: cmn r1, #32768
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; CHECK-ARMNODPS-NEXT: movgt r0, r1
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; CHECK-ARMNODPS-NEXT: bx lr
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; CHECK-ARMNODPS-NEXT: .p2align 2
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; CHECK-ARMNODPS-NEXT: @ %bb.1:
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; CHECK-ARMNODPS-NEXT: .LCPI2_0:
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; CHECK-ARMNODPS-NEXT: .long 4294934528 @ 0xffff8000
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;
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; CHECK-ARMBASEDSP-LABEL: func16:
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; CHECK-ARMBASEDSP: @ %bb.0:
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; CHECK-ARMBASEDSP-NEXT: add r0, r0, r1
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; CHECK-ARMBASEDSP-NEXT: mov r1, #255
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; CHECK-ARMBASEDSP-NEXT: orr r1, r1, #32512
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; CHECK-ARMBASEDSP-NEXT: cmp r0, r1
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; CHECK-ARMBASEDSP-NEXT: movlt r1, r0
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; CHECK-ARMBASEDSP-NEXT: ldr r0, .LCPI2_0
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; CHECK-ARMBASEDSP-NEXT: cmn r1, #32768
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; CHECK-ARMBASEDSP-NEXT: movgt r0, r1
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; CHECK-ARMBASEDSP-NEXT: bx lr
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; CHECK-ARMBASEDSP-NEXT: .p2align 2
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; CHECK-ARMBASEDSP-NEXT: @ %bb.1:
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; CHECK-ARMBASEDSP-NEXT: .LCPI2_0:
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; CHECK-ARMBASEDSP-NEXT: .long 4294934528 @ 0xffff8000
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;
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; CHECK-ARMDSP-LABEL: func16:
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; CHECK-ARMDSP: @ %bb.0:
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; CHECK-ARMDSP-NEXT: qadd16 r0, r0, r1
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; CHECK-ARMDSP-NEXT: sxth r0, r0
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; CHECK-ARMDSP-NEXT: bx lr
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%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y)
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ret i16 %tmp
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}
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@ -284,25 +312,46 @@ define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
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; CHECK-T1-NEXT: .LBB3_4:
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: func8:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: add r0, r1
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; CHECK-T2-NEXT: cmp r0, #127
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; CHECK-T2-NEXT: it ge
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; CHECK-T2-NEXT: movge r0, #127
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; CHECK-T2-NEXT: cmn.w r0, #128
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; CHECK-T2-NEXT: it le
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; CHECK-T2-NEXT: mvnle r0, #127
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; CHECK-T2-NEXT: bx lr
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; CHECK-T2NODSP-LABEL: func8:
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; CHECK-T2NODSP: @ %bb.0:
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; CHECK-T2NODSP-NEXT: add r0, r1
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; CHECK-T2NODSP-NEXT: cmp r0, #127
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; CHECK-T2NODSP-NEXT: it ge
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; CHECK-T2NODSP-NEXT: movge r0, #127
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; CHECK-T2NODSP-NEXT: cmn.w r0, #128
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; CHECK-T2NODSP-NEXT: it le
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; CHECK-T2NODSP-NEXT: mvnle r0, #127
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; CHECK-T2NODSP-NEXT: bx lr
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;
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; CHECK-ARM-LABEL: func8:
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; CHECK-ARM: @ %bb.0:
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; CHECK-ARM-NEXT: add r0, r0, r1
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; CHECK-ARM-NEXT: cmp r0, #127
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; CHECK-ARM-NEXT: movge r0, #127
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; CHECK-ARM-NEXT: cmn r0, #128
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; CHECK-ARM-NEXT: mvnle r0, #127
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; CHECK-ARM-NEXT: bx lr
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; CHECK-T2DSP-LABEL: func8:
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; CHECK-T2DSP: @ %bb.0:
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; CHECK-T2DSP-NEXT: qadd8 r0, r0, r1
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; CHECK-T2DSP-NEXT: sxtb r0, r0
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; CHECK-T2DSP-NEXT: bx lr
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;
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; CHECK-ARMNODPS-LABEL: func8:
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; CHECK-ARMNODPS: @ %bb.0:
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; CHECK-ARMNODPS-NEXT: add r0, r0, r1
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; CHECK-ARMNODPS-NEXT: cmp r0, #127
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; CHECK-ARMNODPS-NEXT: movge r0, #127
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; CHECK-ARMNODPS-NEXT: cmn r0, #128
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; CHECK-ARMNODPS-NEXT: mvnle r0, #127
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; CHECK-ARMNODPS-NEXT: bx lr
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;
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; CHECK-ARMBASEDSP-LABEL: func8:
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; CHECK-ARMBASEDSP: @ %bb.0:
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; CHECK-ARMBASEDSP-NEXT: add r0, r0, r1
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; CHECK-ARMBASEDSP-NEXT: cmp r0, #127
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; CHECK-ARMBASEDSP-NEXT: movge r0, #127
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; CHECK-ARMBASEDSP-NEXT: cmn r0, #128
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; CHECK-ARMBASEDSP-NEXT: mvnle r0, #127
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; CHECK-ARMBASEDSP-NEXT: bx lr
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;
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; CHECK-ARMDSP-LABEL: func8:
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; CHECK-ARMDSP: @ %bb.0:
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; CHECK-ARMDSP-NEXT: qadd8 r0, r0, r1
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; CHECK-ARMDSP-NEXT: sxtb r0, r0
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; CHECK-ARMDSP-NEXT: bx lr
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%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y)
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ret i8 %tmp
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}
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@ -258,29 +258,15 @@ define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounw
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; CHECK-T2DSP-LABEL: func16:
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; CHECK-T2DSP: @ %bb.0:
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; CHECK-T2DSP-NEXT: muls r1, r2, r1
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; CHECK-T2DSP-NEXT: sxtah r0, r0, r1
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; CHECK-T2DSP-NEXT: movw r1, #32767
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; CHECK-T2DSP-NEXT: cmp r0, r1
|
||||
; CHECK-T2DSP-NEXT: it lt
|
||||
; CHECK-T2DSP-NEXT: movlt r1, r0
|
||||
; CHECK-T2DSP-NEXT: movw r0, #32768
|
||||
; CHECK-T2DSP-NEXT: cmn.w r1, #32768
|
||||
; CHECK-T2DSP-NEXT: movt r0, #65535
|
||||
; CHECK-T2DSP-NEXT: it gt
|
||||
; CHECK-T2DSP-NEXT: movgt r0, r1
|
||||
; CHECK-T2DSP-NEXT: qadd16 r0, r0, r1
|
||||
; CHECK-T2DSP-NEXT: sxth r0, r0
|
||||
; CHECK-T2DSP-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func16:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: smulbb r1, r1, r2
|
||||
; CHECK-ARM-NEXT: sxtah r0, r0, r1
|
||||
; CHECK-ARM-NEXT: movw r1, #32767
|
||||
; CHECK-ARM-NEXT: cmp r0, r1
|
||||
; CHECK-ARM-NEXT: movlt r1, r0
|
||||
; CHECK-ARM-NEXT: movw r0, #32768
|
||||
; CHECK-ARM-NEXT: movt r0, #65535
|
||||
; CHECK-ARM-NEXT: cmn r1, #32768
|
||||
; CHECK-ARM-NEXT: movgt r0, r1
|
||||
; CHECK-ARM-NEXT: qadd16 r0, r0, r1
|
||||
; CHECK-ARM-NEXT: sxth r0, r0
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%a = mul i16 %y, %z
|
||||
%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %a)
|
||||
@ -323,23 +309,15 @@ define signext i8 @func8(i8 signext %x, i8 signext %y, i8 signext %z) nounwind {
|
||||
; CHECK-T2DSP-LABEL: func8:
|
||||
; CHECK-T2DSP: @ %bb.0:
|
||||
; CHECK-T2DSP-NEXT: muls r1, r2, r1
|
||||
; CHECK-T2DSP-NEXT: sxtab r0, r0, r1
|
||||
; CHECK-T2DSP-NEXT: cmp r0, #127
|
||||
; CHECK-T2DSP-NEXT: it ge
|
||||
; CHECK-T2DSP-NEXT: movge r0, #127
|
||||
; CHECK-T2DSP-NEXT: cmn.w r0, #128
|
||||
; CHECK-T2DSP-NEXT: it le
|
||||
; CHECK-T2DSP-NEXT: mvnle r0, #127
|
||||
; CHECK-T2DSP-NEXT: qadd8 r0, r0, r1
|
||||
; CHECK-T2DSP-NEXT: sxtb r0, r0
|
||||
; CHECK-T2DSP-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func8:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: smulbb r1, r1, r2
|
||||
; CHECK-ARM-NEXT: sxtab r0, r0, r1
|
||||
; CHECK-ARM-NEXT: cmp r0, #127
|
||||
; CHECK-ARM-NEXT: movge r0, #127
|
||||
; CHECK-ARM-NEXT: cmn r0, #128
|
||||
; CHECK-ARM-NEXT: mvnle r0, #127
|
||||
; CHECK-ARM-NEXT: qadd8 r0, r0, r1
|
||||
; CHECK-ARM-NEXT: sxtb r0, r0
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%a = mul i8 %y, %z
|
||||
%tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %a)
|
||||
|
||||
@ -235,35 +235,63 @@ define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
|
||||
; CHECK-T1-NEXT: .LCPI2_1:
|
||||
; CHECK-T1-NEXT: .long 4294934528 @ 0xffff8000
|
||||
;
|
||||
; CHECK-T2-LABEL: func16:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: subs r0, r0, r1
|
||||
; CHECK-T2-NEXT: movw r1, #32767
|
||||
; CHECK-T2-NEXT: cmp r0, r1
|
||||
; CHECK-T2-NEXT: it lt
|
||||
; CHECK-T2-NEXT: movlt r1, r0
|
||||
; CHECK-T2-NEXT: movw r0, #32768
|
||||
; CHECK-T2-NEXT: cmn.w r1, #32768
|
||||
; CHECK-T2-NEXT: movt r0, #65535
|
||||
; CHECK-T2-NEXT: it gt
|
||||
; CHECK-T2-NEXT: movgt r0, r1
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
; CHECK-T2NODSP-LABEL: func16:
|
||||
; CHECK-T2NODSP: @ %bb.0:
|
||||
; CHECK-T2NODSP-NEXT: subs r0, r0, r1
|
||||
; CHECK-T2NODSP-NEXT: movw r1, #32767
|
||||
; CHECK-T2NODSP-NEXT: cmp r0, r1
|
||||
; CHECK-T2NODSP-NEXT: it lt
|
||||
; CHECK-T2NODSP-NEXT: movlt r1, r0
|
||||
; CHECK-T2NODSP-NEXT: movw r0, #32768
|
||||
; CHECK-T2NODSP-NEXT: cmn.w r1, #32768
|
||||
; CHECK-T2NODSP-NEXT: movt r0, #65535
|
||||
; CHECK-T2NODSP-NEXT: it gt
|
||||
; CHECK-T2NODSP-NEXT: movgt r0, r1
|
||||
; CHECK-T2NODSP-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func16:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: sub r0, r0, r1
|
||||
; CHECK-ARM-NEXT: mov r1, #255
|
||||
; CHECK-ARM-NEXT: orr r1, r1, #32512
|
||||
; CHECK-ARM-NEXT: cmp r0, r1
|
||||
; CHECK-ARM-NEXT: movlt r1, r0
|
||||
; CHECK-ARM-NEXT: ldr r0, .LCPI2_0
|
||||
; CHECK-ARM-NEXT: cmn r1, #32768
|
||||
; CHECK-ARM-NEXT: movgt r0, r1
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
; CHECK-ARM-NEXT: .p2align 2
|
||||
; CHECK-ARM-NEXT: @ %bb.1:
|
||||
; CHECK-ARM-NEXT: .LCPI2_0:
|
||||
; CHECK-ARM-NEXT: .long 4294934528 @ 0xffff8000
|
||||
; CHECK-T2DSP-LABEL: func16:
|
||||
; CHECK-T2DSP: @ %bb.0:
|
||||
; CHECK-T2DSP-NEXT: qsub16 r0, r0, r1
|
||||
; CHECK-T2DSP-NEXT: sxth r0, r0
|
||||
; CHECK-T2DSP-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARMNODPS-LABEL: func16:
|
||||
; CHECK-ARMNODPS: @ %bb.0:
|
||||
; CHECK-ARMNODPS-NEXT: sub r0, r0, r1
|
||||
; CHECK-ARMNODPS-NEXT: mov r1, #255
|
||||
; CHECK-ARMNODPS-NEXT: orr r1, r1, #32512
|
||||
; CHECK-ARMNODPS-NEXT: cmp r0, r1
|
||||
; CHECK-ARMNODPS-NEXT: movlt r1, r0
|
||||
; CHECK-ARMNODPS-NEXT: ldr r0, .LCPI2_0
|
||||
; CHECK-ARMNODPS-NEXT: cmn r1, #32768
|
||||
; CHECK-ARMNODPS-NEXT: movgt r0, r1
|
||||
; CHECK-ARMNODPS-NEXT: bx lr
|
||||
; CHECK-ARMNODPS-NEXT: .p2align 2
|
||||
; CHECK-ARMNODPS-NEXT: @ %bb.1:
|
||||
; CHECK-ARMNODPS-NEXT: .LCPI2_0:
|
||||
; CHECK-ARMNODPS-NEXT: .long 4294934528 @ 0xffff8000
|
||||
;
|
||||
; CHECK-ARMBASEDSP-LABEL: func16:
|
||||
; CHECK-ARMBASEDSP: @ %bb.0:
|
||||
; CHECK-ARMBASEDSP-NEXT: sub r0, r0, r1
|
||||
; CHECK-ARMBASEDSP-NEXT: mov r1, #255
|
||||
; CHECK-ARMBASEDSP-NEXT: orr r1, r1, #32512
|
||||
; CHECK-ARMBASEDSP-NEXT: cmp r0, r1
|
||||
; CHECK-ARMBASEDSP-NEXT: movlt r1, r0
|
||||
; CHECK-ARMBASEDSP-NEXT: ldr r0, .LCPI2_0
|
||||
; CHECK-ARMBASEDSP-NEXT: cmn r1, #32768
|
||||
; CHECK-ARMBASEDSP-NEXT: movgt r0, r1
|
||||
; CHECK-ARMBASEDSP-NEXT: bx lr
|
||||
; CHECK-ARMBASEDSP-NEXT: .p2align 2
|
||||
; CHECK-ARMBASEDSP-NEXT: @ %bb.1:
|
||||
; CHECK-ARMBASEDSP-NEXT: .LCPI2_0:
|
||||
; CHECK-ARMBASEDSP-NEXT: .long 4294934528 @ 0xffff8000
|
||||
;
|
||||
; CHECK-ARMDSP-LABEL: func16:
|
||||
; CHECK-ARMDSP: @ %bb.0:
|
||||
; CHECK-ARMDSP-NEXT: qsub16 r0, r0, r1
|
||||
; CHECK-ARMDSP-NEXT: sxth r0, r0
|
||||
; CHECK-ARMDSP-NEXT: bx lr
|
||||
%tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y)
|
||||
ret i16 %tmp
|
||||
}
|
||||
@ -286,25 +314,46 @@ define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
|
||||
; CHECK-T1-NEXT: .LBB3_4:
|
||||
; CHECK-T1-NEXT: bx lr
|
||||
;
|
||||
; CHECK-T2-LABEL: func8:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: subs r0, r0, r1
|
||||
; CHECK-T2-NEXT: cmp r0, #127
|
||||
; CHECK-T2-NEXT: it ge
|
||||
; CHECK-T2-NEXT: movge r0, #127
|
||||
; CHECK-T2-NEXT: cmn.w r0, #128
|
||||
; CHECK-T2-NEXT: it le
|
||||
; CHECK-T2-NEXT: mvnle r0, #127
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
; CHECK-T2NODSP-LABEL: func8:
|
||||
; CHECK-T2NODSP: @ %bb.0:
|
||||
; CHECK-T2NODSP-NEXT: subs r0, r0, r1
|
||||
; CHECK-T2NODSP-NEXT: cmp r0, #127
|
||||
; CHECK-T2NODSP-NEXT: it ge
|
||||
; CHECK-T2NODSP-NEXT: movge r0, #127
|
||||
; CHECK-T2NODSP-NEXT: cmn.w r0, #128
|
||||
; CHECK-T2NODSP-NEXT: it le
|
||||
; CHECK-T2NODSP-NEXT: mvnle r0, #127
|
||||
; CHECK-T2NODSP-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func8:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: sub r0, r0, r1
|
||||
; CHECK-ARM-NEXT: cmp r0, #127
|
||||
; CHECK-ARM-NEXT: movge r0, #127
|
||||
; CHECK-ARM-NEXT: cmn r0, #128
|
||||
; CHECK-ARM-NEXT: mvnle r0, #127
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
; CHECK-T2DSP-LABEL: func8:
|
||||
; CHECK-T2DSP: @ %bb.0:
|
||||
; CHECK-T2DSP-NEXT: qsub8 r0, r0, r1
|
||||
; CHECK-T2DSP-NEXT: sxtb r0, r0
|
||||
; CHECK-T2DSP-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARMNODPS-LABEL: func8:
|
||||
; CHECK-ARMNODPS: @ %bb.0:
|
||||
; CHECK-ARMNODPS-NEXT: sub r0, r0, r1
|
||||
; CHECK-ARMNODPS-NEXT: cmp r0, #127
|
||||
; CHECK-ARMNODPS-NEXT: movge r0, #127
|
||||
; CHECK-ARMNODPS-NEXT: cmn r0, #128
|
||||
; CHECK-ARMNODPS-NEXT: mvnle r0, #127
|
||||
; CHECK-ARMNODPS-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARMBASEDSP-LABEL: func8:
|
||||
; CHECK-ARMBASEDSP: @ %bb.0:
|
||||
; CHECK-ARMBASEDSP-NEXT: sub r0, r0, r1
|
||||
; CHECK-ARMBASEDSP-NEXT: cmp r0, #127
|
||||
; CHECK-ARMBASEDSP-NEXT: movge r0, #127
|
||||
; CHECK-ARMBASEDSP-NEXT: cmn r0, #128
|
||||
; CHECK-ARMBASEDSP-NEXT: mvnle r0, #127
|
||||
; CHECK-ARMBASEDSP-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARMDSP-LABEL: func8:
|
||||
; CHECK-ARMDSP: @ %bb.0:
|
||||
; CHECK-ARMDSP-NEXT: qsub8 r0, r0, r1
|
||||
; CHECK-ARMDSP-NEXT: sxtb r0, r0
|
||||
; CHECK-ARMDSP-NEXT: bx lr
|
||||
%tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y)
|
||||
ret i8 %tmp
|
||||
}
|
||||
|
||||
@ -245,34 +245,34 @@ define signext i16 @func16(i16 signext %x, i16 signext %y, i16 signext %z) nounw
|
||||
; CHECK-T1-NEXT: .LCPI2_1:
|
||||
; CHECK-T1-NEXT: .long 4294934528 @ 0xffff8000
|
||||
;
|
||||
; CHECK-T2-LABEL: func16:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: muls r1, r2, r1
|
||||
; CHECK-T2-NEXT: sxth r1, r1
|
||||
; CHECK-T2-NEXT: subs r0, r0, r1
|
||||
; CHECK-T2-NEXT: movw r1, #32767
|
||||
; CHECK-T2-NEXT: cmp r0, r1
|
||||
; CHECK-T2-NEXT: it lt
|
||||
; CHECK-T2-NEXT: movlt r1, r0
|
||||
; CHECK-T2-NEXT: movw r0, #32768
|
||||
; CHECK-T2-NEXT: movt r0, #65535
|
||||
; CHECK-T2-NEXT: cmn.w r1, #32768
|
||||
; CHECK-T2-NEXT: it gt
|
||||
; CHECK-T2-NEXT: movgt r0, r1
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
; CHECK-T2NODSP-LABEL: func16:
|
||||
; CHECK-T2NODSP: @ %bb.0:
|
||||
; CHECK-T2NODSP-NEXT: muls r1, r2, r1
|
||||
; CHECK-T2NODSP-NEXT: sxth r1, r1
|
||||
; CHECK-T2NODSP-NEXT: subs r0, r0, r1
|
||||
; CHECK-T2NODSP-NEXT: movw r1, #32767
|
||||
; CHECK-T2NODSP-NEXT: cmp r0, r1
|
||||
; CHECK-T2NODSP-NEXT: it lt
|
||||
; CHECK-T2NODSP-NEXT: movlt r1, r0
|
||||
; CHECK-T2NODSP-NEXT: movw r0, #32768
|
||||
; CHECK-T2NODSP-NEXT: movt r0, #65535
|
||||
; CHECK-T2NODSP-NEXT: cmn.w r1, #32768
|
||||
; CHECK-T2NODSP-NEXT: it gt
|
||||
; CHECK-T2NODSP-NEXT: movgt r0, r1
|
||||
; CHECK-T2NODSP-NEXT: bx lr
|
||||
;
|
||||
; CHECK-T2DSP-LABEL: func16:
|
||||
; CHECK-T2DSP: @ %bb.0:
|
||||
; CHECK-T2DSP-NEXT: muls r1, r2, r1
|
||||
; CHECK-T2DSP-NEXT: qsub16 r0, r0, r1
|
||||
; CHECK-T2DSP-NEXT: sxth r0, r0
|
||||
; CHECK-T2DSP-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func16:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: smulbb r1, r1, r2
|
||||
; CHECK-ARM-NEXT: sxth r1, r1
|
||||
; CHECK-ARM-NEXT: sub r0, r0, r1
|
||||
; CHECK-ARM-NEXT: movw r1, #32767
|
||||
; CHECK-ARM-NEXT: cmp r0, r1
|
||||
; CHECK-ARM-NEXT: movlt r1, r0
|
||||
; CHECK-ARM-NEXT: movw r0, #32768
|
||||
; CHECK-ARM-NEXT: movt r0, #65535
|
||||
; CHECK-ARM-NEXT: cmn r1, #32768
|
||||
; CHECK-ARM-NEXT: movgt r0, r1
|
||||
; CHECK-ARM-NEXT: qsub16 r0, r0, r1
|
||||
; CHECK-ARM-NEXT: sxth r0, r0
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%a = mul i16 %y, %z
|
||||
%tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %a)
|
||||
@ -299,28 +299,31 @@ define signext i8 @func8(i8 signext %x, i8 signext %y, i8 signext %z) nounwind {
|
||||
; CHECK-T1-NEXT: .LBB3_4:
|
||||
; CHECK-T1-NEXT: bx lr
|
||||
;
|
||||
; CHECK-T2-LABEL: func8:
|
||||
; CHECK-T2: @ %bb.0:
|
||||
; CHECK-T2-NEXT: muls r1, r2, r1
|
||||
; CHECK-T2-NEXT: sxtb r1, r1
|
||||
; CHECK-T2-NEXT: subs r0, r0, r1
|
||||
; CHECK-T2-NEXT: cmp r0, #127
|
||||
; CHECK-T2-NEXT: it ge
|
||||
; CHECK-T2-NEXT: movge r0, #127
|
||||
; CHECK-T2-NEXT: cmn.w r0, #128
|
||||
; CHECK-T2-NEXT: it le
|
||||
; CHECK-T2-NEXT: mvnle r0, #127
|
||||
; CHECK-T2-NEXT: bx lr
|
||||
; CHECK-T2NODSP-LABEL: func8:
|
||||
; CHECK-T2NODSP: @ %bb.0:
|
||||
; CHECK-T2NODSP-NEXT: muls r1, r2, r1
|
||||
; CHECK-T2NODSP-NEXT: sxtb r1, r1
|
||||
; CHECK-T2NODSP-NEXT: subs r0, r0, r1
|
||||
; CHECK-T2NODSP-NEXT: cmp r0, #127
|
||||
; CHECK-T2NODSP-NEXT: it ge
|
||||
; CHECK-T2NODSP-NEXT: movge r0, #127
|
||||
; CHECK-T2NODSP-NEXT: cmn.w r0, #128
|
||||
; CHECK-T2NODSP-NEXT: it le
|
||||
; CHECK-T2NODSP-NEXT: mvnle r0, #127
|
||||
; CHECK-T2NODSP-NEXT: bx lr
|
||||
;
|
||||
; CHECK-T2DSP-LABEL: func8:
|
||||
; CHECK-T2DSP: @ %bb.0:
|
||||
; CHECK-T2DSP-NEXT: muls r1, r2, r1
|
||||
; CHECK-T2DSP-NEXT: qsub8 r0, r0, r1
|
||||
; CHECK-T2DSP-NEXT: sxtb r0, r0
|
||||
; CHECK-T2DSP-NEXT: bx lr
|
||||
;
|
||||
; CHECK-ARM-LABEL: func8:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: smulbb r1, r1, r2
|
||||
; CHECK-ARM-NEXT: sxtb r1, r1
|
||||
; CHECK-ARM-NEXT: sub r0, r0, r1
|
||||
; CHECK-ARM-NEXT: cmp r0, #127
|
||||
; CHECK-ARM-NEXT: movge r0, #127
|
||||
; CHECK-ARM-NEXT: cmn r0, #128
|
||||
; CHECK-ARM-NEXT: mvnle r0, #127
|
||||
; CHECK-ARM-NEXT: qsub8 r0, r0, r1
|
||||
; CHECK-ARM-NEXT: sxtb r0, r0
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
%a = mul i8 %y, %z
|
||||
%tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %a)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user