diff --git a/llvm/include/llvm/Target/TargetSchedule.td b/llvm/include/llvm/Target/TargetSchedule.td
index 74b98ac5f6c5..7f92e8b65564 100644
--- a/llvm/include/llvm/Target/TargetSchedule.td
+++ b/llvm/include/llvm/Target/TargetSchedule.td
@@ -55,8 +55,6 @@ include "llvm/Target/TargetItinerary.td"
 
 class Instruction; // Forward def
 
-class Predicate; // Forward def
-
 // DAG operator that interprets the DAG args as Instruction defs.
 def instrs;
 
@@ -99,20 +97,6 @@ class SchedMachineModel {
   // resulting from changes to the instruction definitions.
   bit CompleteModel = 1;
 
-  // A processor may only implement part of published ISA, due to either new ISA
-  // extensions, (e.g. Pentium 4 doesn't have AVX) or implementation
-  // (ARM/MIPS/PowerPC/SPARC soft float cores).
-  //
-  // For a processor which doesn't support some feature(s), the schedule model
-  // can use:
-  //
-  // let<Predicate> UnsupportedFeatures = [HaveA,..,HaveY];
-  //
-  // to skip the checks for scheduling information when building LLVM for
-  // instructions which have any of the listed predicates in their Predicates
-  // field.
-  list<Predicate> UnsupportedFeatures = [];
-
   bit NoModel = 0; // Special tag to indicate missing machine model.
 }
 
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index d1b141e3160f..57a426bffb36 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -120,10 +120,6 @@ CodeGenSchedModels::CodeGenSchedModels(RecordKeeper &RK,
   // (For per-operand resources mapped to itinerary classes).
   collectProcItinRW();
 
-  // Find UnsupportedFeatures records for each processor.
-  // (For per-operand resources mapped to itinerary classes).
-  collectProcUnsupportedFeatures();
-
   // Infer new SchedClasses from SchedVariant.
   inferSchedClasses();
 
@@ -833,15 +829,6 @@ void CodeGenSchedModels::collectProcItinRW() {
   }
 }
 
-// Gather the unsupported features for processor models.
-void CodeGenSchedModels::collectProcUnsupportedFeatures() {
-  for (CodeGenProcModel &ProcModel : ProcModels) {
-    for (Record *Pred : ProcModel.ModelDef->getValueAsListOfDefs("UnsupportedFeatures")) {
-       ProcModel.UnsupportedFeaturesDefs.push_back(Pred);
-    }
-  }
-}
-
 /// Infer new classes from existing classes. In the process, this may create new
 /// SchedWrites from sequences of existing SchedWrites.
 void CodeGenSchedModels::inferSchedClasses() {
@@ -1553,8 +1540,6 @@ void CodeGenSchedModels::checkCompleteness() {
     for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
       if (Inst->hasNoSchedulingInfo)
         continue;
-      if (ProcModel.isUnsupported(*Inst))
-        continue;
       unsigned SCIdx = getSchedClassIdx(*Inst);
       if (!SCIdx) {
         if (Inst->TheDef->isValueUnset("SchedRW") && !HadCompleteModel) {
@@ -1590,10 +1575,7 @@ void CodeGenSchedModels::checkCompleteness() {
       << "- Consider setting 'CompleteModel = 0' while developing new models.\n"
       << "- Pseudo instructions can be marked with 'hasNoSchedulingInfo = 1'.\n"
       << "- Instructions should usually have Sched<[...]> as a superclass, "
-         "you may temporarily use an empty list.\n"
-      << "- Instructions related to unsupported features can be excluded with "
-         "list<Predicate> UnsupportedFeatures = [HasA,..,HasY]; in the "
-         "processor model.\n\n";
+         "you may temporarily use an empty list.\n\n";
     PrintFatalError("Incomplete schedule model");
   }
 }
@@ -1774,16 +1756,6 @@ unsigned CodeGenProcModel::getProcResourceIdx(Record *PRDef) const {
   return 1 + (PRPos - ProcResourceDefs.begin());
 }
 
-bool CodeGenProcModel::isUnsupported(const CodeGenInstruction &Inst) const {
-  for (const Record *TheDef : UnsupportedFeaturesDefs) {
-    for (const Record *PredDef : Inst.TheDef->getValueAsListOfDefs("Predicates")) {
-      if (TheDef->getName() == PredDef->getName())
-        return true;
-    }
-  }
-  return false;
-}
-
 #ifndef NDEBUG
 void CodeGenProcModel::dump() const {
   dbgs() << Index << ": " << ModelName << " "
diff --git a/llvm/utils/TableGen/CodeGenSchedule.h b/llvm/utils/TableGen/CodeGenSchedule.h
index 755ffd25b0cb..7a236ad0dd81 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.h
+++ b/llvm/utils/TableGen/CodeGenSchedule.h
@@ -189,10 +189,6 @@ struct CodeGenProcModel {
   // This list is empty if no ItinRW refers to this Processor.
   RecVec ItinRWDefs;
 
-  // List of unsupported feature.
-  // This list is empty if the Processor has no UnsupportedFeatures.
-  RecVec UnsupportedFeaturesDefs;
-
   // All read/write resources associated with this processor.
   RecVec WriteResDefs;
   RecVec ReadAdvanceDefs;
@@ -215,8 +211,6 @@ struct CodeGenProcModel {
 
   unsigned getProcResourceIdx(Record *PRDef) const;
 
-  bool isUnsupported(const CodeGenInstruction &Inst) const;
-
 #ifndef NDEBUG
   void dump() const;
 #endif
@@ -408,8 +402,6 @@ private:
 
   void collectProcItinRW();
 
-  void collectProcUnsupportedFeatures();
-
   void inferSchedClasses();
 
   void checkCompleteness();